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| 19-5188; Rev 1; 4/10 SFP Controller for Dual Rx Interface General Description The DS1877 controls and monitors all functions for SFF, SFP, and SFP+ modules including all SFF-8472 functionality. The device supports all LOS functions for two receivers, and continually monitors for LOS of either channel. Four ADC channels monitor VCC, temperature, and two differential external monitor inputs that can be used to meet all monitoring requirements. Two digitalto-analog converter (DAC) outputs with temperatureindexed lookup tables (LUTs) are available for additional monitoring and control functionality. Features S Meets All SFF-8472 Control and Monitoring Requirements S Four Analog Monitor Channels: Temperature, VCC, RSSI1, RSSI2 RSSI1 and RSSI2 Support Internal and External Calibration Differential Input Common-Mode Range from GND to VCC Scalable Dynamic Range Internal Direct-to-Digital Temperature Sensor Alarm and Warning Flags for All Monitored Channels S Two 10-Bit Delta-Sigma Outputs Each Controlled by 72-Entry Temperature LUT S Digital I/O Pins: Four Inputs, Four Outputs S Comprehensive Loss-of-Signal (LOS) Detection System S Flexible, Two-Level Password Scheme Provides Three Levels of Security S 120 Bytes of Password-1 Protected Memory S 128 Bytes of Password-2 Protected Memory in Main Device Address S 256 Additional Bytes Located at A0h Slave Address S Receiver 1 is Accessed at A2h Slave Address S Receiver 2 is Accessed at B2h Slave Address S I2C-Compatible Interface S +2.85V to +3.9V Operating Voltage Range S -40NC to +95NC Operating Temperature Range S 28-Pin TQFN (5mm x 5mm x 0.75mm) Package DS1877 Applications SFF, SFP, and SFP+ Transceiver Modules Dual Rx Video SFPs Ordering Information PART DS1877T+ DS1877T+T&R TEMP RANGE -40NC to +95NC -40NC to +95NC PIN-PACKAGE 28 TQFN-EP* 28 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. T&R = Tape and reel. *EP = Exposed pad. _______________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. SFP Controller for Dual Rx Interface DS1877 TABLE OF CONTENTS Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DAC1, DAC2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Analog Voltage Monitoring Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Analog Quick-Trip Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Quick-Trip Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Digital Thermometer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 I2C AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Nonvolatile Memory Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Typical Operating Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 DACs During Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Quick-Trip Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Monitors and Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Two Quick-Trip Monitors and Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Four ADC Monitors and Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 ADC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Right-Shifting ADC Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Differential RSSI1/RSSI2 Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Enhanced RSSI Monitoring (Dual-Range Functionality) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Crossover Enabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Crossover Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Low-Voltage Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Delta-Sigma Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Digital I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 LOS1, LOS2, and LOSOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 INX, RSEL, OUTX, RSELOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 FAULT Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Die Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2 SFP Controller for Dual Rx Interface DS1877 TABLE OF CONTENTS (continued) I2C Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 I2C Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 I2C Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Shadowed EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Memory Map Access Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Memory Addresses A0h, A2h, and B2h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Lower Memory Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 01h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 02h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 04h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 05h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Auxiliary Memory A0h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Lower Memory Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 01h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 02h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 04h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Auxiliary Memory A0h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Power-Supply Decoupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 SDA and SCL Pullup Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3 SFP Controller for Dual Rx Interface DS1877 LIST OF FIGURES Figure 1. Power-Up Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 2. Quick-Trip Sample Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 3. ADC Round-Robin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 4. RSSI1/RSSI2 Differential Input for High-Side RSSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 5. Crossover Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 6. Crossover Disabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 7. Low-Voltage Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 8. Recommended RC Filter for DAC Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 9. 3-Bit (8-Position) Delta-Sigma Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 10. DAC Offset LUTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 11. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 12. I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 13. Example I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 14. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 LIST OF TABLES Table 1. Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 2. ADC Default Monitor Full-Scale Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 3. RSSI1/RSSI2 Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 4. RSSI1/RSSI2 Hysteresis Threshold Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 SFP Controller for Dual Rx Interface ABSOLUTE MAXIMUM RATINGS Voltage Range on RSSI1_, RSSI2_, INX, LOS1, and LOS2 Pins Relative to Ground ...... -0.5V to (VCC + 0.5V)* Voltage Range on VCC, SDA, SCL, OUTX, FAULT, RSELOUT, and LOSOUT Pins Relative to Ground....-0.5V to +6V Continuous Power Dissipation 28-Pin TQFN (derate 34.5mW/NC) above +70NC ....2758.6mW *Subject to not exceeding +6V. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DS1877 Operating Temperature Range .......................... -40NC to +95NC Programming Temperature Range ....................... 0NC to +95NC Storage Temperature Range............................ -55NC to +125NC Lead Temperature (soldering, 10s) ................................+300NC Soldering Temperature (reflow) ......................................+260NC RECOMMENDED OPERATING CONDITIONS (TA = -40NC to +95NC, unless otherwise noted.) PARAMETER Main Supply Voltage High-Level Input Voltage (SDA, SCL) Low-Level Input Voltage (SDA, SCL) High-Level Input Voltage (FAULT, RSEL, INX, LOS1, LOS2) Low-Level Input Voltage (FAULT, RSEL, INX, LOS1, LOS2) SYMBOL VCC VIH:1 VIL:1 (Note 1) CONDITIONS MIN +2.85 0.7 x VCC -0.3 TYP MAX +3.9 VCC + 0.3 0.3 x VCC VCC + 0.3 UNITS V V V VIH:2 2.0 V VIL:2 -0.3 +0.8 V DC ELECTRICAL CHARACTERISTICS (VCC = +2.85V to +3.9V, TA = -40NC to +95NC, unless otherwise noted.) PARAMETER Supply Current Output Leakage (SDA, OUTX, RSELOUT, LOSOUT, FAULT) Low-Level Output Voltage (SDA, OUTX, RSELOUT, LOSOUT, DAC1, DAC2, FAULT) High-Level Output Voltage (DAC1, DAC2) DAC1 and DAC2 Before LUT Recall Input Leakage Current (SCL, RSEL, INX, LOS1, LOS2) Digital Power-On Reset Analog Power-On Reset ILI POD POA 1.0 2.0 SYMBOL ICC ILO IOL = 4mA IOL = 6mA IOH = 4mA VCC 0.4 10 100 1 2.2 2.75 (Notes 1, 2) CONDITIONS MIN TYP 2.5 MAX 10 1 0.4 V 0.6 V nA FA V V 5 UNITS mA FA VOL VOH SFP Controller for Dual Rx Interface DS1877 DAC1, DAC2 ELECTRICAL CHARACTERISTICS (VCC = +2.85V to +3.9V, TA = -40NC to +95NC, unless otherwise noted.) PARAMETER Main Oscillator Frequency Delta-Sigma Input-Clock Frequency Reference Voltage Input (REFIN) Output Range Output Resolution Output Impedance RDS See the Delta-Sigma Outputs section for details 35 SYMBOL fOSC fDS VREFIN Minimum 0.1FF to GND 2 0 CONDITIONS MIN TYP 5 fOSC/2 VCC VREFIN 10 100 MAX UNITS MHz MHz V V Bits I ANALOG VOLTAGE MONITORING CHARACTERISTICS (VCC = +2.85V to +3.9V, TA = -40NC to +95NC, unless otherwise noted.) PARAMETER ADC Resolution Input/Supply Accuracy (RSSI1_, RSSI2_, VCC) Update Rate for Temperature, RSSI1_, RSSI2_, VCC Input/Supply Offset (RSSI1_, RSSI2_, VCC) Factory Setting (Note 4) ACC tRR VOS (Note 3) RSSI1/RSSI2 coarse VCC RSSI1/RSSI2 fine At factory setting SYMBOL CONDITIONS MIN TYP 13 0.25 45 0 2.5 6.5536 312.5 0.5 75 5 MAX UNITS Bits %FS ms LSB V FV AC ELECTRICAL CHARACTERISTICS (VCC = +2.85V to +3.9V, TA = -40NC to +95NC, unless otherwise noted.) PARAMETER Fault Reset Time (to FAULT = 0) LOSOUT Assert Time LOSOUT Deassert Time SYMBOL tINITR tLOSS_ON CONDITIONS From VCC > VCC LO alarm (Note 5) LOS_ LO (Note 6) MIN TYP 161 25.6 25.6 MAX UNITS ms Fs Fs tLOSS_OFF LOS_ HI (Note 7) 6 SFP Controller for Dual Rx Interface ANALOG QUICK-TRIP CHARACTERISTICS (VCC = +2.85V to +3.9V, TA = -40NC to +95NC, unless otherwise noted.) PARAMETER RSSI Full-Scale Voltage Input Resistance Resolution Error Integral Nonlinearity Differential Nonlinearity Temperature Drift Offset TA = +25C -1 -1 -2 -5 35 SYMBOL CONDITIONS MIN TYP 1.25 50 8 2 +1 +1 +2 +10 65 MAX UNITS V kW Bits %FS LSB LSB %FS mV DS1877 QUICK-TRIP TIMING CHARACTERISTICS (VCC = +2.85V to +3.9V, TA = -40NC to +95NC, unless otherwise noted.) PARAMETER Output-Enable Time Following POA Sample Time per Quick-Trip Comparison SYMBOL tINIT tREP (Note 5) CONDITIONS MIN TYP 20 12.8 MAX UNITS ms Fs DIGITAL THERMOMETER CHARACTERISTICS (VCC = +2.85V to +3.9V, TA = -40NC to +95NC, unless otherwise noted.) PARAMETER Thermometer Error SYMBOL TERR CONDITIONS -40NC to +95NC MIN -3 TYP MAX +3 UNITS NC I2C AC ELECTRICAL CHARACTERISTICS (VCC = +2.85V to +3.9V, TA = -40NC to +95NC, unless otherwise noted. Timing is referenced to VIL(MAX) and VIH(MIN).) (Figure 12) PARAMETER SCL Clock Frequency Clock Pulse-Width Low Clock Pulse-Width High Bus Free Time Between STOP and START Condition START Hold Time START Setup Time Data Out Hold Time Data In Setup Time Rise Time of Both SDA and SCL Signals Fall Time of Both SDA and SCL Signals STOP Setup Time Capacitive Load for Each Bus Line EEPROM Write Time SYMBOL fSCL tLOW tHIGH tBUF tHD:STA tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO CB tWR (Note 10) (Note 9) (Note 9) (Note 8) CONDITIONS MIN 0 1.3 0.6 1.3 0.6 0.6 0 100 20 + 0.1CB 20 + 0.1CB 0.6 400 20 300 300 0.9 TYP MAX 400 UNITS kHz Fs Fs Fs Fs Fs Fs ns ns ns Fs pF ms 7 SFP Controller for Dual Rx Interface DS1877 NONVOLATILE MEMORY CHARACTERISTICS (VCC = +2.85V to +3.9V, unless otherwise noted.) PARAMETER EEPROM Write Cycles Note Note Note Note Note Note Note Note Note Note 1: 2: 3: 4: 5: SYMBOL At +25NC At +85NC CONDITIONS MIN 200,000 50,000 TYP MAX UNITS -- All voltages are referenced to ground. Current into the IC is positive, and current out of the IC is negative. Inputs are at supply rail. Outputs are not loaded. This parameter is guaranteed by design. Full-scale is user programmable. A temperature conversion is completed and the DAC values are recalled from the LUTs and VCC has been measured to be above the VCC LO alarm, if the VCC LO alarm is enabled. 6: This specification is the time it takes from RSSI1_ and RSSI2_ voltage falling below the LLOS_ trip threshold to LOSOUT asserted high. 7: This specification is the time it takes from RSSI1_ and RSSI2_ voltage rising above the HLOS_ trip threshold to LOSOUT asserted high. 8: I2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I2C standard mode. 9: CB--Total capacitance of one bus line in pF. 10: EEPROM write begins after a STOP condition occurs. 8 SFP Controller for Dual Rx Interface DS1877 Typical Operating Characteristics (VCC = +3.3V, TA = +25NC, unless otherwise noted.) SUPPLY CURRENT vs. SUPPLY VOLTAGE DS1877 toc01 SUPPLY CURRENT vs. TEMPERATURE 2.45 2.40 SUPPLY CURRENT (mA) 2.35 2.30 2.25 2.20 2.15 2.10 2.05 2.00 2.45 2.40 SUPPLY CURRENT (mA) 2.35 2.30 2.25 2.20 2.15 2.10 2.05 2.00 SDA = SCL = VCC DACs AT 1FFh +95C DAC POSITIONS = 1FFh SDA = SCL = VCC VCC = 3.9V +25C VCC = 3.3V VCC = 2.85V -40C 2.85 3.15 3.45 VCC (V) 3.75 -40 -15 10 35 60 85 TEMPERATURE (C) DAC1/DAC2 DNL DS1877 toc03 DAC1/DAC2 INL DS1877 toc04 1.0 0.8 0.6 DAC1/DAC2 DNL (LSB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 500 DAC POSITION (DEC) 3 2 DAC1/DAC2 INL (LSB) 1 0 -1 -2 -3 1000 0 500 DAC POSITION (DEC) 1000 RSSI1/RSSI2 DNL DS1877 toc05 RSSI1/RSSI2 INL 0.8 0.6 RSSI1/RSSI2 INL (LSB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0.8 0.6 RSSI1/RSSI2 DNL (LSB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 USING FACTORY-PROGRAMMED FULL-SCALE VALUE OF 2.5V USING FACTORY-PROGRAMMED FULL-SCALE VALUE OF 2.5V 0.5 1.0 1.5 2.0 2.5 0 0.5 1.0 1.5 2.0 2.5 RSSI1/RSSI2 INPUT VOLTAGE (V) RSSI1/RSSI2 INPUT VOLTAGE (V) DS1877 toc06 1.0 1.0 DS1877 toc02 2.50 2.50 9 SFP Controller for Dual Rx Interface DS1877 Pin Configuration DAC1 GND DAC2 GND VCC 16 N.C. 15 14 13 12 DS1877 11 10 RSSI1P RSSI2N RSSI2P N.C. DNC RSEL GND 9 8 2 SCL 3 SDA 4 FAULT 5 LOS1 6 INX 7 LOS2 TOP VIEW 21 REFIN 22 N.C. 23 N.C. 24 N.C. 25 VCC 26 LOSOUT 27 OUTX 28 1 RSELOUT 20 19 18 RSSI1N 17 + *EP THIN QFN (5mm x 5mm x 0.8mm) *EXPOSED PAD. Pin Description PIN 1 2 3 4 5 6 7 8, 18, 21 9 10 11, 15, 23, 24, 25 NAME RSELOUT SCL SDA FAULT LOS1 INX LOS2 GND RSEL DNC N.C. FUNCTION Rate-Select Output I2C Serial-Clock Input I2C Serial-Data Input/Output Transmit Fault Input and Output, Open Drain Loss-of-Signal Input 1 Digital Input. General-purpose input, AS1 in SFF-8079, or RS1 in SFF-8431. Loss-of-Signal Input 2 Ground Connection Rate-Select Input Do Not Connect No Connection. Not internally connected. -- EP 28 OUTX PIN 12, 13 14, 17 16, 26 19 20 22 27 NAME RSSI2P, RSSI2N RSSI1P, RSSI1N VCC DAC2 DAC1 REFIN LOSOUT FUNCTION Differential External Monitor Input 2 and LOS2 LO Quick Trip Differential External Monitor Input 1 and LOS1 LO Quick Trip Power-Supply Input DAC2, Delta-Sigma Output DAC1, Delta-Sigma Output Reference Input for DAC1 and DAC2 Receive Loss-of-Signal Output Digital Output. General-purpose output, AS1 output in SFF-8079, or RS1 output in SFF-8431. Exposed Pad (Connect to GND) 10 SFP Controller for Dual Rx Interface Block Diagram DS1877 VCC VCC SDA SCL I2C INTERFACE REFIN MAIN MEMORY AT A2h/B2h EEPROM/SRAM A/D CONFIGURATION/RESULTS, SYSTEM STATUS/CONTROL BITS, ALARMS/WARNINGS, LOOKUP TABLES, USER MEMORY 10-BIT DELTA-SIGMA DAC DAC1 EEPROM 256 BYTES AT A0h 10-BIT DELTA-SIGMA DAC DAC2 VCC RSSI1P ANALOG MUX RSSI1N RSSI2P RSSI2N TEMPERATURE SENSOR RSELOUT RSEL 13-BIT ADC 8-BIT QTs DS1877 POWER-ON ANALOG INTERRUPT FAULT INX LOGIC CONTROL LOS1 OUTX LOSOUT LOS2 GND 11 SFP Controller for Dual Rx Interface DS1877 Typical Operating Circuit +3.3V R ROUT2+ ROUT2- RX2 THRESH2 +3.3V R LOS2 RX1 RC FILTERS THRESH1 ROUT1+ ROUT1- LOS1 DAC1 DAC2 DS1877 EEPROM LOS1 LOS2 FAULT LOSOUT FAULT LOS MODE_DEF2 (SDA) MODE_DEF1 (SCL) LOS RSSI1 RSSI2 ADC I2C SDA SCL 12 SFP Controller for Dual Rx Interface Detailed Description The DS1877 integrates the control and monitoring functionality required in an SFP or SFP+ system. The device is specifically designed for a dual-receiver SFP module. Key components of the device are shown in the Block Diagram and described in subsequent sections. On power-up, the device sets the DACs to high impedance. After time tINIT, the DACs are set to an initial condition set in EEPROM. After a temperature conversion is completed and if the VCC LO alarm is enabled, an additional VCC conversion above the customer-defined VCC LO alarm level is required before the DACs are updated with the value determined by the temperature conversion and the DAC LUT. See Figure 1. As shown in Figure 2, the device's input comparator is shared between two LOS comparisons. The comparator polls the alarms in a multiplexed sequence. The comparator checks the LOS (RSSI1_ and RSSI2_) signals against the internal reference. Depending on the results of the comparison, the corresponding alarms and warnings are asserted or deasserted. Any QT alarm that is detected by default remains active until a subsequent comparator sample shows that the condition no longer exists. Table 1. Acronyms ACRONYM ADC AGC APC APD ATB DAC LOS LUT NV QT TIA ROSA SEE SFF SFF-8472 SFP SFP+ DESCRIPTION Analog-to-Digital Converter Automatic Gain Control Automatic Power Control Avalanche Photodiode Alarm Trap Bytes Digital-to-Analog Converter Loss of Signal Lookup Table Nonvolatile Quick Trip Transimpedance Amplifier Receiver Optical Subassembly Shadowed EEPROM Small Form Factor Document Defining Register Map of SFPs and SFFs Small Form Factor Pluggable Enhanced SFP DS1877 DACs During Power-Up Quick-Trip Timing VPOA VCC 500s tINIT DAC SETTINGS HIGH IMPEDANCE OFF STATE LUT VALUE Figure 1. Power-Up Timing QUICK-TRIP SAMPLE TIMES LOS2 LOS1 LOS2 LOS1 tREP Figure 2. Quick-Trip Sample Timing 13 SFP Controller for Dual Rx Interface DS1877 Monitors and Fault Detection Monitors Monitoring functions on the device include two QT comparators and four ADC channels. This monitoring combined with the alarm enables (Table 01h/05h) determines when/if the device triggers the FAULT and/or LOSOUT outputs. All the monitoring levels and interrupt masks are user programmable. Two Quick-Trip Monitors and Alarms Two quick-trip monitors are provided that monitor the following: 1) Loss of signal 1 (LOS1 LO) 2) Loss of signal 2 (LOS2 LO) The LOS_ LO QTs compare the RSSI_ input against its threshold setting to determine if the present received power is below the specification. The LOS_ LO QT can be used to set the LOSOUT pin. Four ADC Monitors and Alarms The ADC monitors 4 channels that measure temperature (internal temp sensor), VCC, RSSI1, and RSSI2 using an analog multiplexer to measure them round-robin with a single ADC (see the ADC Timing section). The 3V channels have a customer-programmable full-scale range, and all channels have a customer-programmable offset value that is factory programmed to a default value (see Table 2). Additionally, RSSI1 and RSSI2 can right-shift results by up to 7 bits before the results are compared to alarm thresholds or read over the I2C bus. This allows customers with specified ADC ranges to calibrate the ADC full scale to a factor of 1/2n of their specified range to measure small signals. The device can then right-shift the results by n bits to maintain the bit weight of their specification (see the Right-Shifting ADC Result section). The ADC results (after right-shifting, if used) are compared to the alarm and warning thresholds after each conversion, and the corresponding alarms are set that can be used to trigger the FAULT output. These ADC thresholds are user programmable, as are the masking registers that can be used to prevent the alarms from triggering the FAULT output. ADC Timing There are four analog channels that are digitized in a round-robin fashion in the order as shown in Figure 3. The total time required to convert all 4 channels is tRR (see the Analog Voltage Monitoring Characteristics for details). Right-Shifting ADC Result If the weighting of the ADC digital reading must conform to a predetermined full-scale (PFS) value defined by a standard's specification (e.g., SFF-8472), then rightshifting can be used to adjust the PFS analog measurement range while maintaining the weighting of the ADC results. The device's range is wide enough to cover all requirements; when the maximum input value is P 1/2 the FS value, right-shifting can be used to obtain greater accuracy. For instance, the maximum voltage might be 1/8 the specified PFS value, so only 1/8 of the converter's range is effective over this range. An alternative is to calibrate the ADC's full-scale range to 1/8 the readable PFS value and use a right-shift value of 3. With this implementation, the resolution of the measurement is increased by Table 2. ADC Default Monitor Full-Scale Ranges SIGNAL (UNITS) Temperature (NC) VCC (V) RSSI1, RSSI2 (V) +FS SIGNAL 127.996 6.5528 2.4997 +FS HEX 7FFF FFF8 FFF8 -FS SIGNAL -128 0 0 -FS HEX 8000 0000 0000 ONE ROUND-ROBIN ADC CYCLE TEMP VCC RSSI1 FINE tRR NOTE: IF THE VCC LO ALARM IS ENABLED AT POWER-UP, THE ADC ROUND-ROBIN TIMING CYCLES BETWEEN TEMPERATURE AND VCC ONLY UNTIL VCC IS ABOVE THE VCC LO ALARM THRESHOLD. RSSI1 COARSE RSSI2 FINE RSSI2 COARSE TEMP Figure 3. ADC Round-Robin Timing 14 SFP Controller for Dual Rx Interface a factor of 8, and because the result is digitally divided by 8 by right-shifting, the bit weight of the measurement still meets the standard's specification (i.e., SFF-8472). The right-shift operation on the ADC result is carried out based on the contents of right-shift control registers (Table 02h, Registers 8Eh-8Fh) in EEPROM. Two analog channels--RSSI1 and RSSI2--each have 3 bits allocated to set the number of right-shifts. Up to seven right-shift operations are allowed and are executed as a part of every conversion before the results are compared to the high and low alarm levels, or loaded into their corresponding measurement registers (Lower Memory, Registers 64h to 6Bh). This is true during the setup of internal calibration as well as during subsequent data conversions. Differential RSSI1/RSSI2 Inputs The device offers fully differential inputs for RSSI1 and RSSI2. This enables high-side monitoring of RSSI, as shown in Figure 4. It also reduces board complexity by VCC RSSI_P R RSSI_N DS1877 ADC eliminating the need for a high-side differential amplifier or a current mirror. Enhanced RSSI Monitoring (Dual-Range Functionality) The device offers a feature to improve the accuracy and range of RSSI1/RSSI2, which is most commonly used for monitoring RSSI. Using a traditional input, the RSSI measurement accuracy can be increased at the cost of reduced input signal swing. The device eliminates this trade-off by offering "dual-range" calibration on the RSSI1/RSSI2 channels. The dual-range calibration can operate in two modes: crossover enabled and crossover disabled. Dual-range operation is enabled by default (factory programmed in EEPROM). However, it can easily be disabled by the RSSIn_FC and RSSIn_FF bits (where n can be 1 or 2) in 8Dh, Table 02h. Dual-range functionality consists of two ADC modes of operation: fine mode and coarse mode. Each mode is calibrated for a unique transfer function, hence the term, dual range. Table 3 highlights the registers related to RSSI1/RSSI2. Fine mode is calibrated using the gain, offset, and right-shifting registers at locations shown in Table 3, and is ideal for relatively small analog-input voltages. Coarse mode is automatically switched to when the input exceeds a threshold. Coarse mode is calibrated using different gain and offset registers from fine mode. The gain and offset registers for coarse mode are also shown in Table 3. Additional information for each of the registers can be found in the memory map (Figure 14). DS1877 ROSA Figure 4. RSSI1/RSSI2 Differential Input for High-Side RSSI Table 3. RSSI1/RSSI2 Configuration Registers REGISTER RSSI1/RSSI2 Gain (RSSI1/2 FINE/COARSE SCALE) RSSI1/RSSI2 Offset (RSSI1/2 FINE/COARSE OFFSET) Right-Shift (RSHIFT1, RSHIFT2) Crossover (XOVER1/XOVER2 FINE/COARSE) FORCE RSSI (RSSIn_FC and RSSIn_FF Bits) UPDATE (RSSIR Bit) RSSI VALUE (RSSI1/RSSI2 Measurement) FINE MODE 9Eh-9Fh/9Ah-9Bh, Table 02h AEh-AFh/AAh-ABh, Table 02h 8Eh-8Fh, Table 02h A6h-A7h/96h-97h, Table 02h 8Dh, Table 02h 6Fh, Lower Memory 68h-69h, Lower Memory COARSE MODE 9Ch-9Dh/98h-99h, Table 02h ACh-ADh/A8h-A9h, Table 02h 8Eh-8Fh, Table 02h A4h-A5h/94h-95Fh, Table 02h 15 SFP Controller for Dual Rx Interface Dual-range operation is transparent to the end user. The results of RSSI1/RSSI2 ADCs are still stored/reported in the same memory locations (68h-69h, Lower Memory) regardless of whether the conversion was performed in fine mode or coarse mode. The RSSIR bit indicates whether a fine or coarse conversion generated the digital result. When the device is powered up, ADCs begin in a roundrobin fashion. Every RSSI1/RSSI2 time slice begins with a fine mode ADC (using fine mode's gain, offset, and right-shifting settings). If the value is too large for a fine conversion, a coarse conversion is performed and the result is reported. The coarse-mode conversion is performed using the coarse gain and offset settings. The intersection between coarse and fine depends on the crossover mode used. The RSSIn_FC and RSSIn_FF bits are used to force fine-mode or coarse-mode conversions or to disable the dual-range functionality. Dual-range functionality is enabled by default (both RSSIn_FC and RSSIn_FF are factory programmed to 0 in EEPROM). Dual-range functionality can be disabled by setting RSSIn_FC to 0 and RSSIn_FF to 1. These bits are also useful when calibrating RSSI1/RSSI2. See the register descriptions and memory map for additional information. Crossover Enabled For systems with a nonlinear relationship between the ADC input and desired ADC result, the mode should be set to crossover enabled (Figure 5). The RSSI measurement of an APD receiver is one such application. Using the crossover-enabled mode allows a piecewise linear approximation of the nonlinear response of the APD's gain factor. The crossover point is the value where the fine and coarse ranges intersect. The ADC result transitions between the fine and coarse ranges as defined by the XOVER registers. Right-shifting, slope adjustment, and offset are configurable for both the fine and coarse ranges. The XOVER1/XOVER2 FINE registers determine the maximum results returned by the fine ADC conversions before right-shifting. The XOVER1/ XOVER2 COARSE registers determine the minimum results returned by coarse ADC conversions before right-shifting. Crossover Disabled The crossover-disabled mode is intended for systems with a linear relationship between the RSSI1/RSSI2 input and the desired ADC result. The ADC result transitions DS1877 between the fine and coarse ranges with hysteresis, as shown in Figure 6. In crossover-disabled mode, the thresholds between coarse and fine mode are a function of the number of right-shifts being used. With the use of right-shifting, the fine-mode full scale is programmed to (1/2nth) of the coarse-mode full scale. The device now automatically ranges to choose the range that gives the best resolution for the measurement. Table 4 shows the threshold values for each possible number of right-shifts. The device contains two power-on reset (POR) levels. The lower level is a digital POR (POD) and the higher level is an analog POR (POA). At startup, before the supply voltage rises above POA, the outputs are disabled, all SRAM locations are set to their defaults, shadowed EEPROM (SEE) locations are zero, and all analog circuitry is disabled. When VCC reaches POA, the SEE is recalled, and the analog circuitry is enabled. While VCC remains above POA, the device is in its normal operating state, and it responds based on its nonvolatile configuration. If during operation VCC falls below POA, but is still above POD, the SRAM retains the SEE settings from the first SEE recall, but the device analog is shut down and the outputs disabled. If the supply voltage recovers back above POA, the device immediately resumes normal operation. If the supply voltage falls below POD, the device SRAM is placed in its default state and another SEE recall is required to reload the nonvolatile settings. The EEPROM recall occurs the next time VCC next exceeds POA. Figure 7 shows the sequence of events as the voltage varies. Low-Voltage Operation Table 4. RSSI1/RSSI2 Hysteresis Threshold Values NO. OF RIGHTSHIFTS 0 1 2 3 4 5 6 7 FINE MODE MAX (HEX) FFF8 7FFC 3FFE 1FFF 0FFF 07FF 03FF 01FF COARSE MODE MIN* (HEX) F000 7800 3C00 1E00 0F00 0780 03C0 01E0 *This is the minimum reported coarse-mode conversion. 16 SFP Controller for Dual Rx Interface DS1877 RSSI RESULT CROSSOVER POINT IDEAL RESPONSE RSSI_ INPUT Figure 5. Crossover Enabled RSSI RESULT PON SE ALE L-SC CO SHI FT =3 HYSTERESIS FINE FUL A E RS FU LL- SC R ALE ESP FIN ER TIGH RES ON SE RSSI_ INPUT FINE COARSE Figure 6. Crossover Disabled SEE RECALL VPOA VCC VPOD SEE RECALL SEE PRECHARGED TO 0 RECALLED VALUE PRECHARGED TO 0 RECALLED VALUE PRECHARGED TO 0 Figure 7. Low-Voltage Operation 17 SFP Controller for Dual Rx Interface Any time VCC is above POD, the I2C interface can be used to determine if VCC is below the POA level. This is accomplished by checking the RDYB bit in the STATUS byte (Lower Memory, Register 6Eh). RDYB is set when VCC is below POA; when VCC rises above POA, RDYB is timed (within 500Fs) to go to 0, at which point the part is fully functional. For all device addresses sourced from EEPROM (Table 02h, Register 8Bh), the default device address is A2h until VCC exceeds POA, allowing the device address to be recalled from the EEPROM. The device's delta-sigma outputs are 10 bits. For illustrative purposes, a 3-bit example is provided in Figure 8. 3.24k DAC 0.01F DS1877 3.24k VOLTAGE OUTPUT 0.01F DS1877 Each possible output of this 3-bit delta-sigma DAC is provided in Figure 9. In LUT mode the DACs are each controlled by an LUT with high-temperature resolution and an OFFSET LUT with lower temperature resolution. The high-resolution LUTs each have 2NC resolutions. The OFFSET LUTs are located in the upper eight registers (F8h-FFh, Table 04h) of the table containing each high-resolution LUT. The DAC values are determined as follows: DAC value = DAC LUT + 4 x (DAC OFFSET LUT) An example calculation for DAC1 is as follows: Assumptions: 1) Temperature is +43NC 2) Table 04h (DAC OFFSET LUT), Register FCh = 2Ah 3) Table 04h (DAC LUT), Register AAh = 7Bh Because the temperature is +43NC, the DAC LUT index is AAh and the DAC1 OFFSET LUT index is FCh. DAC1 = 7Bh + 4 x 2Ah = 123h = 291 When temperature controlled, the DACs are updated after each temperature conversion. See Figure 10. Delta-Sigma Outputs 1k DAC 1k CURRENT SINK 0.1F 0.1F 2k DS1877 The reference input, REFIN, is the supply voltage for the output buffer of all the DACs. The voltage connected to REFIN must be able to support the edge rate requirements of the delta-sigma outputs. In a typical application, a 0.1FF capacitor should be connected between REFIN and ground. Figure 8. Recommended RC Filter for DAC Outputs O 1 2 3 4 5 6 7 Figure 9. 3-Bit (8-Position) Delta-Sigma Example 18 SFP Controller for Dual Rx Interface DS1877 DAC OFFSET LUTs (04h)[A2h/B2h] EIGHT REGISTERS PER DAC EACH OFFSET REGISTER CAN BE INDEPENDENTLY SET BETWEEN 0 AND 1020. 1020 = 4 x FFh. THIS EXAMPLE ILLUSTRATES POSITIVE TEMPCO. FDh FCh FBh 511 F8h 255 DAC LUT BITS 7:0 F9h DAC LUT BITS 7:0 FAh DAC LUT BITS 7:0 DAC LUT BITS 7:0 DAC LUT BITS 7:0 DAC LUT BITS 7:0 FFh FEh DAC LUT BITS 7:0 DAC LUT BITS 7:0 DELTA-SIGMA DACs DAC OFFSET LUTs (04h/06h)[A2h/B2h] EIGHT REGISTERS PER DAC EACH OFFSET REGISTER CAN BE INDEPENDENTLY SET BETWEEN 0 AND 1020. 1020 = 4 x FFh. THIS EXAMPLE ILLUSTRATES POSITIVE AND NEGATVE TEMPCO. FDh DAC LUT BITS 7:0 1023 1023 767 DELTA-SIGMA DACs 767 FBh FAh 511 F8h 255 DAC LUT BITS 7:0 F9h DAC LUT BITS 7:0 DAC LUT BITS 7:0 DAC LUT BITS 7:0 FCh DAC LUT BITS 7:0 FEh DAC LUT BITS 7:0 FFh DAC LUT BITS 7:0 0 -40C -8C +8C +24C +40C +56C +70C +88C +104C 0 -40C -8C +8C +24C +40C +56C +70C +88C +104C Figure 10. DAC Offset LUTs LOSC1 LOS1 MUX INVLOS1 LOS LO1 INVLOSOUT LOSOUT Four digital input pins and four digital output pins are provided for monitoring and control. LOS1, LOS2, and LOSOUT When LOSC_ = 0 (Table 02h, Register 8Ah), the LOS_ pin is used to convert a standard comparator output for LOS to an open-collector output. The output of the mux can be read in the STATUS register (Lower Memory, Register 6Eh) as the RXL bit. The RXL signal can be inverted (INVLOS_ = 1) before driving the open-drain output transistor using the XOR gate provided. Setting LOSC_ = 1 configures the mux to be controlled by the LOS LO QT alarm. The mux setting (stored in EEPROM) does not take effect until VCC > POA, allowing the EEPROM to recall. INX, RSEL, OUTX, RSELOUT Digital input pins INX and RSEL primarily serve to meet the rate-select requirements of SFP and SFP+. They can also serve as general-purpose inputs. OUT1 and RSELOUT are driven by a combination of the INX, RSEL, and logic dictated by control registers in the EEPROM (see Figure 11). The levels of INX and RSEL can be read from the STATUS register (Lower Memory, Register 6Eh). The open-drain output OUTX can be controlled and/or inverted using the CNFGB register (Table 02h, Register 89h). The open-drain RSELOUT output is software controlled and/or inverted through the STATUS register and Digital I/O Pins LOSC2 LOS2 MUX INVLOS2 LOS LO2 RXL IN1S INVOUT1 IN1C IN1 INVRSOUT RSELS RSELC RSEL = PINS OUT1 RSELOUT Figure 11. Logic Diagram 19 SFP Controller for Dual Rx Interface DS1877 CNFGA register (Table 02h, Register 88h). External pullup resistors must be provided on OUTX and RSELOUT to realize high logic levels. FAULT Output FAULT can be triggered by all alarms, warnings, and QTs. The six ADC alarms, warnings, and LOS QTs require enabling (Table 01h/05h, Registers F8h and FCh). Latching of the alarms is controlled by the CNFGB and CNFGC registers (Table 02h, Registers 89h-8Ah). The device has an ID hardcoded in its die. Two registers (Table 02h, Registers 86h-87h) are assigned for this feature. Register 86h reads 77h to identify the part as the DS1877; Register 87h reads the present device version. Bus Idle or Not Busy: Time between STOP and START conditions when both SDA and SCL are inactive and in their logic-high states. START Condition: A START condition is generated by the master to initiate a new data transfer with a slave. Transitioning SDA from high to low while SCL remains high generates a START condition. See Figure 12 for applicable timing. STOP Condition: A STOP condition is generated by the master to end a data transfer with a slave. Transitioning SDA from low to high while SCL remains high generates a STOP condition. See Figure 12 for applicable timing. Repeated START Condition: The master can use a repeated START condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. Repeated STARTs are commonly used during read operations to identify a specific memory address to begin a data transfer. A repeated START condition is issued identically to a normal START condition. See Figure 12 for applicable timing. Bit Write: Transitions of SDA must occur during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse Die Identification I2C Communication The following terminology is commonly used to describe I2C data transfers. I2C Definitions Master Device: The master device controls the slave devices on the bus. The master device generates SCL clock pulses and START and STOP conditions. Slave Devices: Slave devices send and receive data at the master's request. SDA tBUF tF tLOW SCL tHD:STA tSP tHD:STA tR tHD:DAT tHIGH tSU:DAT REPEATED START tSU:STA tSU:STO STOP START NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN). Figure 12. I2C Timing 20 SFP Controller for Dual Rx Interface of SCL plus the setup and hold time requirements (Figure 12). Data is shifted into the device during the rising edge of the SCL. Bit Read: At the end of a write operation, the master must release the SDA bus line for the proper amount of setup time (Figure 12) before the next rising edge of SCL during a bit read. The device shifts out each bit of data on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. Remember that the master generates all SCL clock pulses, including when it is reading bits from the slave. Acknowledgement (ACK and NACK): An acknowledgement (ACK) or not-acknowledge (NACK) is always the 9th bit transmitted during a byte transfer. The device receiving data (the master during a read or the slave during a write operation) performs an ACK by transmitting a zero during the 9th bit. A device performs a NACK by transmitting a one during the 9th bit. Timing (Figure 12) for the ACK and NACK is identical to all other bit writes. An ACK is the acknowledgment that the device is properly receiving data. A NACK is used to terminate a read sequence or as an indication that the device is not receiving data. Byte Write: A byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from the slave to the master. The 8 bits transmitted by the master are done according to the bit write definition and the acknowledgement is read using the bit read definition. Byte Read: A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK or NACK from the master to the slave. The 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition, and the master transmits an ACK using the bit write definition to receive additional data bytes. The master must NACK the last byte read to terminate communication so the slave returns control of SDA to the master. Slave Address Byte: Each slave on the I2C bus responds to a slave address byte sent immediately following a START condition. The slave address byte contains the slave address in the most significant 7 bits and the R/W bit in the least significant bit. The device responds to three slave addresses. The auxiliary memory always responds to a fixed I2C slave address, A0h. (If the main device's slave address is programmed to be A0h/B0h, access to the auxiliary memory is disabled.) The Lower Memory and Tables 00h-05h respond to I2C slave addresses whose lower 3 bits are configurable (A0h-AEh, B0h-BEh) using the DEVICE ADDRESS byte (Table 02h, Register 8Bh). The user also must set the ASEL bit (Table 02h, Register 88h) for this address to be active. By writing the correct slave address with R/W = 0, the master indicates it writes data to the slave. If R/W = 1, the master reads data from the slave. If an incorrect slave address is written, the device assumes the master is communicating with another I2C device and ignores the communications until the next START condition is sent. Memory Address: During an I2C write operation to the device, the master must transmit a memory address to identify the memory location where the slave is to store the data. The memory address is always the second byte transmitted during a write operation following the slave address byte. See Figure 13 for an example of I2C timing. DS1877 I2C Protocol Writing a Single Byte to a Slave: The master must generate a START condition, write the slave address byte (R/W = 0), write the memory address, write the byte of data, and generate a STOP condition. Remember that the master must read the slave's acknowledgement during all byte write operations. Writing Multiple Bytes to a Slave: To write multiple bytes to a slave, the master generates a START condition, writes the slave address byte (R/W = 0), writes the memory address, writes up to 8 data bytes, and generates a STOP condition. The device writes 1 to 8 bytes (one page or row) with a single write transaction. This is internally controlled by an address counter that allows data to be written to consecutive addresses without transmitting a memory address before each data byte is sent. The address counter limits the write to one 8-byte page (one row of the memory map). Attempts to write to additional pages of memory without sending a STOP condition between pages result in the address counter wrapping around to the beginning of the present row. For example: A 3-byte write starts at address 06h and writes three data bytes (11h, 22h, and 33h) to three "consecutive" addresses. The result is that addresses 06h and 07h would contain 11h and 22h, respectively, and the third data byte, 33h, would be written to address 00h. 21 SFP Controller for Dual Rx Interface DS1877 TYPICAL I2C WRITE TRANSACTION MSB START X X X X SLAVE ADDRESS* 0 0 1 LSB R/W READ/ WRITE SLAVE ACK MSB b7 b6 b5 b4 b3 b2 b1 LSB b0 SLAVE ACK MSB b7 b6 b5 b4 b3 b2 b1 LSB b0 SLAVE ACK STOP REGISTER ADDRESS DATA *IF ASEL IS 0, THE SLAVE ADDRESS IS A0h FOR THE AUXILIARY MEMORY AND A2h/B2h FOR THE MAIN MEMORY. IF ASEL = 1, THE SLAVE ADDRESS IS DETERMINED BY TABLE 02h, REGISTER 8Bh FOR THE MAIN MEMORY. THE AUXILIARY MEMORY CONTINUES TO BE ADDRESSED AT A0h, EXCEPT WHEN THE PROGRAMMED ADDRESS FOR THE MAIN MEMORY IS A0h. EXAMPLE I2C TRANSACTIONS WITH A2h AS THE MAIN MEMORY DEVICE ADDRESS A2h A) SINGLE-BYTE WRITE -WRITE 00h TO REGISTER BAh START 1 0 1 0 0 0 1 0 BAh 00h SLAVE SLAVE SLAVE 1 0 1 1 1 0 1 0 ACK 0 0 0 0 0 0 0 0 ACK ACK STOP B) SINGLE-BYTE READ -READ REGISTER BAh A2h BAh START 1 0 1 0 0 0 1 0 SLAVE 1 0 1 1 1 0 1 0 SLAVE ACK ACK REPEATED START A3h 1 0 1 0 0 0 1 1 SLAVE ACK DATA DATA IN BAh MASTER NACK STOP C) TWO-BYTE WRITE -WRITE 01h AND 75h TO REGISTERS C8h AND C9h A2h C8h 01h 75h START 1 0 1 0 0 0 1 0 SLAVE 1 1 0 0 1 0 0 0 SLAVE 0 0 0 0 0 0 0 1 SLAVE 0 1 1 1 0 1 0 1 SLAVE ACK ACK ACK ACK A2h C8h START 1 0 1 0 0 0 1 0 SLAVE 1 1 0 0 1 0 0 0 SLAVE ACK ACK A3h 1 0 1 0 0 0 1 1 SLAVE ACK DATA STOP DATA MASTER ACK DATA IN C9h MASTER NACK STOP D) TWO-BYTE READ -READ C8h AND C9h REPEATED START DATA IN C8h Figure 13. Example I2C Timing To prevent address wrapping from occurring, the master must send a STOP condition at the end of the page, then wait for the bus-free or EEPROM write time to elapse. Then the master can generate a new START condition and write the slave address byte (R/W = 0) and the first memory address of the next memory row before continuing to write data. Acknowledge Polling: Any time a EEPROM page is written, the device requires the EEPROM write time (tWR) after the STOP condition to write the contents of the page to EEPROM. During the EEPROM write time, the device does not acknowledge its slave address because it is busy. It is possible to take advantage of that phenomenon by repeatedly addressing the device, which allows the next page to be written as soon as the device is ready to receive the data. The alternative to acknowledge polling is to wait for maximum period of tWR to elapse before attempting to write again to the device. EEPROM Write Cycles: When EEPROM writes occur, the device writes the whole EEPROM memory page, even if only a single byte on the page was modified. Writes that do not modify all 8 bytes on the page are allowed and do not corrupt the remaining bytes of memory on the same page. Because the whole page is written, bytes on the page that were not modified during the transaction are still subject to a write cycle. This can result in a whole page being worn out over time by writing a single byte repeatedly. Writing a page 1 byte at a time wears the EEPROM out 8x faster than writing the entire page at once. The device's EEPROM write cycles are specified in the Nonvolatile Memory Characteristics table. The specification shown is at the worst-case temperature. It can handle approximately 10x that many writes at room temperature. Writing to SRAM-shadowed EEPROM memory with SEEB = 1 does not count as a EEPROM write cycle when evaluating the EEPROM's estimated lifetime. 22 SFP Controller for Dual Rx Interface Reading a Single Byte from a Slave: Unlike the write operation that uses the memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. To read a single byte from the slave, the master generates a START condition, writes the slave address byte with R/W = 1, reads the data byte with a NACK to indicate the end of the transfer, and generates a STOP condition. Manipulating the Address Counter for Reads: A dummy write cycle can be used to force the address pointer to a particular value. To do this, the master generates a START condition, writes the slave address byte (R/W = 0), writes the memory address where it desires to read, generates a repeated START condition, writes the slave address byte (R/W = 1), reads data with ACK or NACK as applicable, and generates a STOP condition. range. It also contains an LUT for temperature-controlled offsets for DAC1. Table 05h, A2h is empty by default. It can be configured to contain the alarm and warning enable bytes from Table 01h, Registers F8h-FFh with the MASK bit enabled (Table 02h, Register 88h). In this case Table 01h is empty. The main device located at B2h is used for receiver 2 control, calibration, alarms, warnings, and monitoring. Lower Memory, B2h is addressed from 00h-7Fh and contains alarm and warning thresholds, flags, masks, several control registers, PWE, and the table-select byte. Table 01h, B2h contains alarm and warning enable bytes. Table 02h, B2h is a multifunction space that contains configuration registers, scaling and offset values, passwords, interrupt registers as well as other miscellaneous control bytes. Table 02h, B2h only contains functions related to receiver 2. All other functions are controlled by Table 02h, A2h. Table 04h, B2h contains a temperature-indexed LUT for control of the DAC2 voltage. The DAC2 LUT can be programmed in 2NC increments over the -40NC to +102NC range. It also contains an LUT for temperature-controlled offsets for DAC2. Table 05h, B2h is empty by default. It can be configured to contain the alarm and warning-enable bytes from Table 01h, Registers F8h-FFh with the MASK bit enabled (Table 02h, Register 88h). In this case Table 01h is empty. Auxiliary Memory (Device A0h) contains 256 bytes of EE memory accessible from address 00h-FFh. It is selected with the device address of A0h. See the Register Descriptions section for a more complete detail of each byte's function, as well as for read/ write permissions for each byte. DS1877 Memory Organization The device features memory tables that are internally organized into 8-byte rows. The main device located at A2h is used for overall device configuration and receiver 1 control, calibration, alarms, warnings, and monitoring. Lower Memory, A2h is addressed from 00h-7Fh and contains alarm and warning thresholds, flags, masks, several control registers, password entry area (PWE), and the table-select byte. Table 01h, A2h primarily contains user EEPROM (with PW1 level access) as well as alarm and warning enable bytes. Table 02h, A2h is a multifunction space that contains configuration registers, scaling and offset values, passwords, and interrupt registers as well as other miscellaneous control bytes. Table 04h, A2h contains a temperature-indexed LUT for control of the DAC1 voltage. The DAC1 LUT can be programmed in 2NC increments over the -40NC to +102NC 23 SFP Controller for Dual Rx Interface DS1877 I2C ADDRESS A0h 00h I2C ADDRESS A2h/B2h 00h LOWER MEMORY PASSWORD ENTRY (PWE) (4 BYTES) TABLE-SELECT BYTE 7Fh NOTE 1: IF ASEL = 0, THEN THE MAIN DEVICE I2C SLAVE ADDRESS IS A2h/B2h. IF ASEL = 1, THEN THE MAIN DEVICE I2C SLAVE ADDRESS IS DETERMINED BY THE VALUE IN TABLE 02h, REGISTER 8Bh. A0h AND B2h ARE INVALID SELECTIONS. NOTE 2: TABLE 00h DOES NOT EXIST. NOTE 3: ALARM-ENABLE ROW CAN BE CONFIGURED TO EXIST AT TABLE 01h OR TABLE 05h USING THE MASK BIT IN TABLE 02h, REGISTER 88h. MAIN DEVICES AT A2h AND B2h EEPROM (256 BYTES) AUXILIARY DEVICE 80h 80h TABLE 02h TABLE 01h EEPROM (120 BYTES) NONLOOKUP TABLE CONTROL AND CONFIGURATION REGISTERS F7h (B2h ONLY CONTAINS RECEIVER 2RELATED REGISTERS) FFh 80h TABLE 04h DAC1 (A2h) DAC2 (B2h) LOOKUP TABLE (72 BYTES) C7h ALARM-ENABLE ROW CAN BE CONFIGURED TO EXIST AT TABLE 01h OR TABLE 05h USING MASK BIT IN TABLE 02h, REGISTER 88h. F8h FFh ALARMENABLE ROW (8 BYTES) FFh F8h DAC1/2 OFFSET LUT FFh F8h TABLE 05h ALARM-ENABLE ROW (8 BYTES) FFh Figure 14. Memory Map Many nonvolatile memory locations (listed within the Register Descriptions section) are actually shadowed EEPROM and are controlled by the SEEB bit in Table 02h, Register 80h. Shadowed EEPROM The device incorporates shadowed EEPROM memory locations for key memory addresses that can be written many times. By default the shadowed EEPROM bit, SEEB, is not set and these locations act as ordinary EEPROM. By setting SEEB, these locations function like SRAM cells, which allow an infinite number of write cycles without concern of wearing out the EEPROM. This also eliminates the requirement for the EEPROM write time, tWR. Because changes made with SEEB enabled do not affect the EEPROM, these changes are not retained through power cycles. The power-on value is the last value written with SEEB disabled. This function can be used to limit the number of EEPROM writes during calibration or to change the monitor thresholds periodically during normal operation helping to reduce the number of times EEPROM is written. Figure 14 shows the memory map and indicates which locations are shadowed EEPROM. 24 SFP Controller for Dual Rx Interface Register Descriptions The register maps show each byte/word (2 bytes) in terms of its row in the memory. The first byte in the row is located in memory at the row address (hexadecimal) in the leftmost column. Each subsequent byte on the row is one/two memory locations beyond the previous byte/ word's address. A total of 8 bytes are present on each row. For more information about each of these bytes, see the corresponding register description. The following section provides the device's register definitions. Each register or row of registers has an access descriptor that determines the password level required to read or write the memory. Level 2 password is intended for the module manufacture access only. Level 1 password allows another level of protection for items the end consumer wishes to protect. Many registers are always readable, but require password access to write. There are a few registers that cannot be read without password access. The following access codes describe each mode the device uses with factory settings for the PW_ENA and PW_ENB (Table 02h, Registers C0h-C1h) registers. ACCESS CODE <0/_> <1/_> <2/_> READ ACCESS WRITE ACCESS There are three separate I2C addresses in the device: A0h, A2h, and B2h. A2h and B2h are used to configure and monitor two receivers. Receiver 1 is accessed using A2h. Receiver 2 is accessed using B2h. Many of the registers in A2h and B2h are shared registers. These registers can be read and written from both A2h and B2h. MEMORY CODE Memory Addresses A0h, A2h, and B2h DS1877 Memory Map Access Codes At least 1 byte/bit in the row/byte is different than the rest of the row/byte, so look at each byte/bit separately for permissions. Read all Read all Write PW2 Write not applicable Write all, but the device hardware also writes to these bytes/bits Write PW2 + mode_bit Write all Write all Write PW1 Write PW2 Write PW2 Write not applicable Write PW1 <3/_> Read all <4/_> <5/_> <6/_> <7/_> <8/_> <9/_> <10/_> <11/_> Read PW2 Read all Read not applicable Read PW1 Read PW2 Read not applicable Read PW2 Read all 25 SFP Controller for Dual Rx Interface DS1877 Lower Memory Register Map LOWER MEMORY ROW (HEX) 00-07 08-0F 10-1F 20-27 28-37 38-4F 50-5F 60-67 68-6F 70-77 78-7F ROW NAME <1/C>THRESHOLD WORD 0 BYTE 0/8 0 1 BYTE 1/9 WORD 1 BYTE 2/A BYTE 3/B WORD 2 BYTE 4/C BYTE 5/D BYTE 6/E WORD 3 BYTE 7/F TEMP ALARM HI VCC ALARM HI EE TEMP ALARM LO VCC ALARM LO EE RSSI ALARM LO EE EE TEMP WARN HI VCC WARN HI EE RSSI WARN HI EE EE TEMP WARN LO VCC WARN LO EE RSSI WARN LO EE EE EE EE RESERVED <0/M>STATUS <3/D>UPDATE <1/C >THRESHOLD <1/C>EEPROM <1/D>THRESHOLD <1/C >EEPROM <1/D >EEPROM <1/C >EEPROM <2/C>ADC <0/M>ADC 4 RSSI ALARM HI EE EE EE TEMP VALUE <2/D> EE EE VCC VALUE RESERVED RESERVED RESERVED EE EE RESERVED RESERVED WARN3 MSW EE VALUES0 VALUES1 RSSI VALUE ALARM2 RESERVED <5/D>ALARM/WARN <0/M>TABLE ALARM3 RESERVED ALARM0 <6/C>PWE RESERVED <6/C>PWE RESERVED LSW RESERVED <5/D>TBL SELECT SEL Table 01h Register Map TABLE 01h ROW (HEX) 80-BF C0-F7 F8-FF ROW NAME <7/C>EEPROM <8/C>EEPROM <7/M>ALARM WORD 0 BYTE 0/8 EE EE WORD 1 BYTE 1/9 EE EE BYTE 2/A EE EE EN2 RESERVED BYTE 3/B EE EE WORD 2 BYTE 4/C EE EE EN0 WORD 3 BYTE 6/E EE EE RESERVED BYTE 7/F EE EE RESERVED BYTE 5/D EE EE ENABLE EN3 EN3 RESERVED The access codes represent the factory default values of PW_ENA and PW_ENB (Table 02h, Registers C0h-C1h). These registers also allow for custom permissions. ACCESS CODE Read Access Write Access <0/_> <1/_> All <2/_> All <3/_> All All and DS1877 Hardware <4/_> PW2 PW2 + mode bit <5/_> All <6/_> N/A <7/_> PW1 <8/_> PW2 <9/_> N/A <10/_> PW2 <11/_> All See each bit/byte separately PW2 N/A All All PW1 PW2 PW2 N/A PW1 26 SFP Controller for Dual Rx Interface DS1877 Table 02h Register Map TABLE 02h (PW2) ROW (HEX) 80 88 90 98 A0 A8 B0 B8 C0 C8 D0-FF ROW NAME <0/C>CONFIG WORD 0 BYTE 0/8 <8/C>MODE WORD 1 BYTE 1/9 BYTE 2/A RESERVED CNFGC BYTE 3/B RESERVED DEVICE ADDRESS WORD 2 BYTE 4/C RESERVED RESERVED BYTE 5/D RESERVED FORSE RSSI BYTE 6/E <10>DEVICE WORD 3 BYTE 7/F ID <10>DEVICE 0 1 <4/C>TINDEX VER <8/C>CONFIG <8/C>SCALE <8/C>SCALE CNFGA CNFGB RSHIFT2 RSHIFT1 0 1 0 1 RESERVED RSSI2 COARSE SCALE INTERNAL TEMP OFFSET* RSSI2 COARSE OFFSET PW1 MSW LOS RANGING2 PW_ENA RESERVED PW_ENB VCC SCALE RSSI2 FINE SCALE VCC OFFSET RSSI2 FINE OFFSET PW1 LSW HLOS2 RESERVED LLOS2 RESERVED XOVER2 COARSE RSSI1 COARSE SCALE XOVER2 COARSE RSSI1 COARSE OFFSET PW2 MSW LOS RANGING1 RESERVED RESERVED RESERVED XOVER2 FINE RSSI1 FINE SCALE XOVER1 FINE RSSI1 FINE OFFSET PW2 LSW HLOS1 POLARITY LLOS1 TBLSELPON <8/C>OFFSET <8/C>OFFSET <9/C>PWD VALUE <8/C>THRESHOLD <8/C>PWD <4/C>DAC ENABLE VALUES DAC2 VALUE EMPTY EMPTY EMPTY RESERVED EMPTY DAC1 VALUE EMPTY EMPTY EMPTY RESERVED EMPTY EMPTY Table 04h Register Map TABLE 04h (DAC LUT) ROW (HEX) 80-C7 C8-F7 F8-FF ROW NAME <8/D>LUT4 WORD 0 BYTE 0/8 DAC LUT EMPTY DAC OFFSET LUT BYTE 1/9 DAC LUT EMPTY DAC OFFSET LUT WORD 1 BYTE 2/A DAC LUT EMPTY DAC OFFSET LUT BYTE 3/B DAC LUT EMPTY DAC OFFSET LUT WORD 2 BYTE 4/C DAC LUT EMPTY DAC OFFSET LUT BYTE 5/D DAC LUT EMPTY DAC OFFSET LUT BYTE 6/E DAC LUT EMPTY WORD 3 BYTE 7/F DAC LUT EMPTY DAC OFFSET LUT EMPTY <8/D>DAC OFFSET DAC OFFSET LUT The access codes represent the factory default values of PW_ENA and PW_ENB (Table 02h, Registers C0h-C1h). These registers also allow for custom permissions. ACCESS CODE Read Access Write Access <0/_> <1/_> All <2/_> All <3/_> All All and DS1877 Hardware <4/_> PW2 PW2 + mode bit <5/_> All <6/_> N/A <7/_> PW1 <8/_> PW2 <9/_> N/A <10/_> PW2 <11/_> All See each bit/byte separately PW2 N/A All All PW1 PW2 PW2 N/A PW1 27 SFP Controller for Dual Rx Interface DS1877 Table 05h Register Map TABLE 05h ROW (HEX) 80-F7 F8-FF ROW NAME EMPTY <7/M>ALARM WORD 0 BYTE 0/8 EMPTY WORD 1 BYTE 1/9 EMPTY BYTE 2/A EMPTY EN2 RESERVED BYTE 3/B EMPTY WORD 2 BYTE 4/C EMPTY EN0 WORD 3 BYTE 6/E EMPTY RESERVED BYTE 7/F EMPTY RESERVED BYTE 5/D EMPTY RESERVED ENABLE EN3 EN3 Auxiliary Memory A0h Register Map AUXILIARY MEMORY (A0h) ROW (HEX) 00-FF ROW NAME <5>AUX WORD 0 BYTE 0/8 EE BYTE 1/9 EE WORD 1 BYTE 2/A EE BYTE 3/B EE WORD 2 BYTE 4/C EE BYTE 5/D EE BYTE 6/E EE WORD 3 BYTE 7/F EE EE The access codes represent the factory default values of PW_ENA and PW_ENB (Table 02h, Registers C0h-C1h). These registers also allow for custom permissions. ACCESS CODE Read Access Write Access <0/_> <1/_> All <2/_> All <3/_> All All and DS1877 Hardware <4/_> PW2 PW2 + mode bit <5/_> All <6/_> N/A <7/_> PW1 <8/_> PW2 <9/_> N/A <10/_> PW2 <11/_> All See each bit/byte separately PW2 N/A All All PW1 PW2 PW2 N/A PW1 28 SFP Controller for Dual Rx Interface Lower Memory Register Descriptions Lower Memory, Register 00h-01h: TEMP ALARM HI Lower Memory, Register 04h-05h: TEMP WARN HI FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 00h, 04h 01h, 05h S 2-1 BIT 7 26 2-2 7FFFh All PW2 or (PW1 and WLOWER) Common A2h and B2h memory locations Nonvolatile (SEE) 25 2-3 24 2-4 23 2-5 22 2-6 21 2-7 20 2-8 BIT 0 DS1877 Temperature measurement updates above this two's complement threshold set its corresponding alarm or warning bit. Temperature measurement updates equal to or below this threshold clear its alarm or warning bit. Lower Memory, Register 02h-03h: TEMP ALARM LO Lower Memory, Register 06h-07h: TEMP WARN LO FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 02h, 06h 03h, 07h S 2-1 BIT 7 26 2-2 8000h All PW2 or (PW1 and WLOWER) Common A2h and B2h memory locations Nonvolatile (SEE) 25 2-3 24 2-4 23 2-5 22 2-6 21 2-7 20 2-8 BIT 0 Temperature measurement updates below this two's complement threshold set its corresponding alarm or warning bit. Temperature measurement updates equal to or above this threshold clear its alarm or warning bit. 29 SFP Controller for Dual Rx Interface DS1877 Lower Memory, Register 08h-09h: VCC ALARM HI Lower Memory, Register 0Ch-0Dh: VCC WARN HI FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 08h, 0Ch 09h, 0Dh 215 27 BIT 7 214 26 FFFFh All PW2 or (PW1 and WLOWER) Common A2h and B2h memory locations Nonvolatile (SEE) 213 25 212 24 211 23 210 22 29 21 28 20 BIT 0 Voltage measurement updates above this unsigned threshold set its corresponding alarm or warning bit. Voltage measurements equal to or below this threshold clear its alarm or warning bit. Lower Memory, Register 0Ah-0Bh: VCC ALARM LO Lower Memory, Register 0Eh-0Fh: VCC WARN LO FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 0Ah, 0Eh 0Bh, 0Fh 215 27 BIT 7 214 26 0000h All PW2 or (PW1 and WLOWER) Common A2h and B2h memory locations Nonvolatile (SEE) 213 25 212 24 211 23 210 22 29 21 28 20 BIT 0 Voltage measurement updates below this unsigned threshold set its corresponding alarm or warning bit. Voltage measurements equal to or above this threshold clear its alarm or warning bit. Lower Memory, Register 10h-1Fh: EE FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 10h-1Fh EE BIT 7 PW2 level access-controlled EEPROM. EE 00h All PW2 or (PW1 and WLOWER) Common A2h and B2h memory locations Nonvolatile (EE) EE EE EE EE EE EE BIT 0 30 SFP Controller for Dual Rx Interface DS1877 Lower Memory, Register 20h-21h: RSSI ALARM HI Lower Memory, Register 24h-25h: RSSI WARN HI FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 215 27 BIT 7 214 26 FFFFh All PW2 or (PW1 and WLOWER) Different A2h and B2h memory locations Nonvolatile (SEE) 213 25 212 24 211 23 210 22 29 21 28 20 BIT 0 20h, 24h 21h, 25h Voltage measurement updates above this unsigned threshold set its corresponding alarm or warning bit. Voltage measurements equal to or below this threshold clear its alarm or warning bit. Lower Memory, Register 22h-23h: RSSI ALARM LO Lower Memory, Register 26h-27h: RSSI WARN LO FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 215 27 BIT 7 214 26 0000h All PW2 or (PW1 and WLOWER) Different A2h and B2h memory locations Nonvolatile (SEE) 213 25 212 24 211 23 210 22 29 21 28 20 BIT 0 22h, 26h 23h, 27h Voltage measurement updates below this unsigned threshold set its corresponding alarm or warning bit. Voltage measurements equal to or above this threshold clear its alarm or warning bit. 31 SFP Controller for Dual Rx Interface DS1877 Lower Memory, Register 28h-37h: EE FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 28h-37h EE BIT 7 PW2 level access-controlled EEPROM. EE 00h All PW2 or (PW1 and WLOWER) Common A2h and B2h memory locations Nonvolatile (EE) EE EE EE EE EE EE BIT 0 Lower Memory, Register 38h-4Fh: EE FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 38h-4Fh EE BIT 7 PW2 level access-controlled EEPROM. EE 00h All PW2 or (PW1 and WLOWER) Different A2h and B2h memory locations Nonvolatile (EE) EE EE EE EE EE EE BIT 0 Lower Memory, Register 50h-5Fh: EE FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 50h-5Fh EE BIT 7 PW2 level access-controlled EEPROM. EE 00h All PW2 or (PW1 and WLOWER) Common A2h and B2h memory locations Nonvolatile (EE) EE EE EE EE EE EE BIT 0 32 SFP Controller for Dual Rx Interface DS1877 Lower Memory, Register 60h-61h: TEMP VALUE FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 60h 61h S 2-1 BIT 7 Signed two's complement direct-to-temperature measurement. 26 2-2 0000h All N/A Common A2h and B2h memory locations Volatile 25 2-3 24 2-4 23 2-5 22 2-6 21 2-7 20 2-8 BIT 0 Lower Memory, Register 62h-63h: VCC VALUE POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 62h 63h 215 27 BIT 7 Left-justified unsigned voltage measurement. 214 26 0000h All N/A Common A2h and B2h memory locations Volatile 213 25 212 24 211 23 210 22 29 21 28 20 BIT 0 Lower Memory, Register 64h-67h: RESERVED POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 64h-67h 0 BIT 7 These registers are reserved. The value when read is 00h. 0 00h N/A N/A N/A N/A 0 0 0 0 0 0 BIT 0 33 SFP Controller for Dual Rx Interface DS1877 Lower Memory, Register 68h-69h: RSSI VALUE POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 68h 69h 215 27 BIT 7 Left-justified unsigned voltage measurement. 214 26 0000h All N/A Different A2h and B2h memory locations Volatile 213 25 212 24 211 23 210 22 29 21 28 20 BIT 0 Lower Memory, Register 6Ah-6Dh: RESERVED POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 6Ah-6Dh 0 BIT 7 These registers are reserved. The value when read is 00h. 0 00h N/A N/A N/A N/A 0 0 0 0 0 0 BIT 0 34 SFP Controller for Dual Rx Interface Lower Memory, Register 6Eh: STATUS POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE Write Access 6Eh N/A RESERVED BIT 7 BIT 7 RESERVED TXDC1 [A2h]: TXD1 software control bit (writable by all users). 0 = (default) This bit has no effect on alarms and warnings. 1 = Setting TXDC1 inhibits the latching of low alarms and warnings LOS1 LO, LOS2 LO, RSSI1 LO, and RSSI2 LO after the condition is cleared. Once TXDC1 is set, it is internally extended by time tINITR to allow for settings to stabilize. Clearing TXDC1 before tINITR has no impact on the latching of these alarms and warnings. TXDC2 [B2h]: TXD2 software control bit (writable by all users). 0 = (default) This bit has no effect on alarms and warnings. 1 = Setting TXDC2 inhibits the latching of low alarms and warnings LOS1 LO, LOS2 LO, RSSI1 LO, and RSSI2 LO after the condition is cleared. Once TXDC2 is set, it is internally extended by time tINITR to allow for settings to stabilize. Clearing TXDC2 before tINITR has no impact on the latching of these alarms and warnings. INXS [A2h or B2h]: INX status bit. Reflects the logic state of the INX pin (read-only). 0 = INX pin is logic-low. 1 = INX pin is logic-high. RSELS [A2h or B2h]: RSEL status bit. Reflects the logic state of the RSEL pin (read-only). 0 = RSEL pin is logic-low. 1 = RSEL pin is logic-high. RSELC [A2h or B2h]: RSEL software control bit. This bit allows for software control that is identical to the RSEL pin. Its value is wire-ORed with the logic value of the RSEL pin to create the RSELOUT pin's logic value (writable by all users). 0 = (default) 1 = Forces the device into a RSEL state regardless of the value of the RSEL pin. FLTS: Reflects the driven state of the FAULT pin (read-only). 0 = FAULT pin is low. 1 = FAULT pin is high. RXL1 [A2h]: Status of LOS1 pin or LOS1 LO as determined by the LOSC control bit. RXL2 [B2h]: Status of LOS2 pin or LOS2 LO as determined by the LOSC control bit. RDYB [A2h or B2h]: Ready bar. 0 = VCC is above POA. 1 = VCC is below POA and/or too low to communicate over the I2C bus. All <5/D>TXDC DS1877 X0XX 0XXXb All See below Mixture of common memory locations and different memory locations (see below) Volatile N/A <2/C>INXS All <2/C>RSELS All <5/C>RSELC N/A <2/C>FLTS N/A <2/D>RXL N/A <2/C>RDYB BIT 0 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 35 SFP Controller for Dual Rx Interface DS1877 Lower Memory, Register 6Fh: UPDATE POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 6Fh TEMP RDY BIT 7 VCC RDY 00h All All and device hardware Different A2h and B2h memory locations Volatile RESERVED RESERVED RSSI RDY RESERVED RESERVED RSSIR BIT 0 TEMP RDY, VCC RDY, RSSI RDY: Update of completed conversions. At power-on, these bits are cleared and are set as each conversion is completed. These bits can be cleared so that a completion of a new conversion is verified. RESERVED RSSIR: RSSI range. Reports the range used for conversion update of RSSI. 0 = Fine range is the reported value. 1 = Coarse range is the reported value. BITS 7, 6, 3 BITS 5, 4, 2, 1 BIT 0 Lower Memory, Register 70h: ALARM3 POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 70h TEMP HI BIT 7 TEMP HI: High alarm status for temperature measurement. 0 = (default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. TEMP LO: Low alarm status for temperature measurement. 0 = (default) Last measurement was equal to or above threshold setting. 1 = Last measurement was below threshold setting. VCC HI: High alarm status for VCC measurement. 0 = (default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. VCC LO: Low alarm status for VCC measurement. This bit is set when the VCC supply is below the POA trip point value. It clears itself when a VCC measurement is completed and the value is above the low threshold. 0 = Last measurement was equal to or above threshold setting. 1 = (default) Last measurement was below threshold setting. RESERVED TEMP LO 10h All N/A Different A2h and B2h memory locations Volatile VCC HI VCC LO RESERVED RESERVED RESERVED RESERVED BIT 0 BIT 7 BIT 6 BIT 5 BIT 4 BITS 3:0 36 SFP Controller for Dual Rx Interface Lower Memory, Register 71h: ALARM2 POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 71h RSSI HI BIT 7 RSSI HI: High alarm status for RSSI measurement. A TXD event does not clear this alarm. 0 = (default) Last measurement was equal to or below the threshold setting. 1 = Last measurement was above the threshold setting. RSSI LO: Low alarm status for RSSI measurement. A TXD event does not clear this alarm. 0 = (default) Last measurement was equal to or below the threshold setting. 1 = Last measurement was above the threshold setting. RESERVED FLTINT: FAULT interrupt. This bit is the wire-ORed logic of all alarms and warnings wire-ANDed with their corresponding enable bits. The enable bits are found in Table 01h/05h, Registers F8h-FFh. RSSI LO 00h All N/A Mixed A2h and B2h memory locations Volatile RESERVED RESERVED RESERVED RESERVED RESERVED FLTINT BIT 0 DS1877 BIT 7 BIT 6 BITS 5:1 BIT 0 Lower Memory, Register 72h: RESERVED POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE This register is reserved. 00h N/A N/A N/A N/A 37 SFP Controller for Dual Rx Interface DS1877 Lower Memory, Register 73h: ALARM0 POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 73h LOS HI BIT 7 LOS LO 00h All N/A Different A2h and B2h memory locations Volatile RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED BIT 0 LOS HI: High alarm status for RSSI; fast comparison. A TXD event does not clear this alarm. 0 = (default) Last comparison was below threshold setting. 1 = Last comparison was above threshold setting. LOS LO: Low alarm status for RSSI; fast comparison. A TXD event does not clear this alarm. 0 = (default) Last comparison was above threshold setting. 1 = Last comparison was below threshold setting. RESERVED BIT 7 BIT 6 BITS 5:0 Lower Memory, Register 74h: WARN3 POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 74h TEMP HI BIT 7 TEMP HI: High warning status for temperature measurement. 0 = (default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. TEMP LO: Low warning status for temperature measurement. 0 = (default) Last measurement was equal to or above threshold setting. 1 = Last measurement was below threshold setting. VCC HI: High warning status for VCC measurement. 0 = (default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. VCC LO: Low warning status for VCC measurement. This bit is set when the VCC supply is below the POA trip-point value. It clears itself when a VCC measurement is completed and the value is above the low threshold. 0 = Last measurement was equal to or above threshold setting. 1 = (default) Last measurement was below threshold setting. RESERVED TEMP LO 10h All N/A Different A2h and B2h memory locations Volatile VCC HI VCC LO RESERVED RESERVED RESERVED RESERVED BIT 0 BIT 7 BIT 6 BIT 5 BIT 4 BITS 3:0 38 SFP Controller for Dual Rx Interface Lower Memory, Registers 75h-7Ah: RESERVED POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 00h N/A N/A N/A N/A DS1877 These registers are reserved. The value when read is 00h. Lower Memory, Registers 7Bh-7Eh: PASSWORD ENTRY (PWE) POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 7Bh 7Ch 7Dh 7Eh 231 223 215 27 BIT 7 230 222 214 26 FFFF FFFFh N/A All Common A2h and B2h memory locations Volatile 229 221 213 25 228 220 212 24 227 219 211 23 226 218 210 22 225 217 29 21 224 216 28 20 BIT 0 There are two passwords for the device. Each password is 4 bytes long. The lower level password (PW1) has all the access of a normal user plus those made available with PW1. The higher level password (PW2) has all the access of PW1 plus those made available with PW2. The values of the passwords reside in EEPROM inside PW2 memory. At power-up, all PWE bits are set to 1. All reads at this location are 0. Lower Memory, Register 7Fh: TABLE SELECT (TBL SEL) POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 7Fh 27 BIT 7 26 TBLSELPON (Table 02h, Register C7h) All All Different A2h and B2h memory locations Volatile 25 24 23 22 21 20 BIT 0 The upper memory tables of the device are accessible by writing the desired table value in this register. The poweron value of this register is defined by the value written to TBLSELPON (Table 02h, Register C7h). 39 SFP Controller for Dual Rx Interface DS1877 Table 01h Register Descriptions Table 01h, Register 80h-F7h: EEPROM POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 80h-F7h EE BIT 7 EEPROM for PW1 and/or PW2 level access. EE 00h PW2 or (PW1 and RWTBL1A) or (PW1 and RTBL1A) PW2 or (PW1 and RWTBL1A) Common A2h and B2h memory locations Nonvolatile (EE) EE EE EE EE EE EE BIT 0 Table 01h, Register F8h: ALARM EN3 POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE F8h TEMP HI BIT 7 TEMP LO 00h PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C) PW2 or (PW1 and RWTBL1C) Common A2h and B2h memory locations Nonvolatile (SEE) VCC HI VCC LO RESERVED RESERVED RESERVED RESERVED BIT 0 Layout is identical to ALARM3 in Lower Memory, Register 70h. Enables alarms to create FLTINT (Lower Memory, Register 71h) logic. The MASK bit (Table 02h, Register 88h) determines whether this memory exists in Table 01h or 05h. BIT 7 TEMP HI [A2h or B2h]: 0 = Disables interrupt from TEMP HI alarm. 1 = Enables interrupt from TEMP HI alarm. TEMP LO [A2h or B2h]: 0 = Disables interrupt from TEMP LO alarm. 1 = Enables interrupt from TEMP LO alarm. VCC HI [A2h or B2h]: 0 = Disables interrupt from VCC HI alarm. 1 = Enables interrupt from VCC HI alarm. VCC LO [A2h or B2h]: 0 = Disables interrupt from VCC LO alarm. 1 = Enables interrupt from VCC LO alarm. RESERVED BIT 6 BIT 5 BIT 4 BITS 3:0 40 SFP Controller for Dual Rx Interface Table 01h, Register F9h: ALARM EN2 POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE F9h RSSI HI BIT 7 RSSI LO 00h PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C) PW2 or (PW1 and RWTBL1C) Different A2h and B2h memory locations Nonvolatile (SEE) RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED BIT 0 DS1877 Layout is identical to ALARM2 in Lower Memory, Register 71h. Enables alarms to create FLTINT (Lower Memory, Register 71h). The MASK bit (Table 02h, Register 88h) determines whether this memory exists in Table 01h or 05h. BIT 7 RSSI HI: 0 = Disables interrupt from RSSI HI alarm. 1 = Enables interrupt from RSSI HI alarm. RSSI LO: 0 = Disables interrupt from RSSI LO alarm. 1 = Enables interrupt from RSSI LO alarm. RESERVED BIT 6 BITS 5:0 Table 01h, Register FAh: RESERVED POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE This register is reserved. 00h N/A N/A N/A N/A 41 SFP Controller for Dual Rx Interface DS1877 Table 01h, Register FBh: ALARM EN0 POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE FBh LOS HI BIT 7 LOS LO 00h PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C) PW2 or (PW1 and RWTBL1C) Different A2h and B2h memory locations Nonvolatile (SEE) RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED BIT 0 Layout is identical to ALARM1 in Lower Memory, Register 73h. The MASK bit (Table 02h, Register 88h) determines whether this memory exists in Table 01h or 05h. BIT 7 LOS HI: Enables alarm to create FLTINT (Lower Memory, Register 71h) logic. 0 = Disables interrupt from LOS HI alarm. 1 = Enables interrupt from LOS HI alarm. LOS LO: Enables alarm to create FLTINT (Lower Memory, Register 71h) logic. 0 = Disables interrupt from LOS LO alarm. 1 = Enables interrupt from LOS LO alarm. RESERVED BIT 6 BITS 5:0 Table 01h, Register FCh: WARN EN3 POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE FCh TEMP HI BIT 7 TEMP LO 00h PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C) PW2 or (PW1 and RWTBL1C) Common A2h and B2h memory locations Nonvolatile (SEE) VCC HI VCC LO RESERVED RESERVED RESERVED RESERVED BIT 0 Layout is identical to WARN3 in Lower Memory, Register 74h. Enables warnings to create FLTINT (Lower Memory, Register 71h) logic. The MASK bit (Table 02h, Register 88h) determines whether this memory exists in Table 01h or 05h. BIT 7 TEMP HI [A2h or B2h]: 0 = Disables interrupt from the TEMP HI warning. 1 = Enables interrupt from the TEMP HI warning. TEMP LO [A2h or B2h]: 0 = Disables interrupt from the TEMP LO warning. 1 = Enables interrupt from the TEMP LO warning. VCC HI [A2h or B2h]: 0 = Disables interrupt from the VCC HI warning. 1 = Enables interrupt from the VCC HI warning. VCC LO [A2h or B2h]: 0 = Disables interrupt from the VCC LO warning. 1 = Enables interrupt from the VCC LO warning. RESERVED BIT 6 BIT 5 BIT 4 BITS 3:0 42 SFP Controller for Dual Rx Interface Table 01h, Register FDh-FFh: RESERVED POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 00h N/A N/A N/A N/A DS1877 These registers are reserved. Table 02h Register Descriptions Table 02h, Register 80h: MODE POWER-ON VALUE READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 80h SEEB BIT 7 DAC2EN 7Fh PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) PW2 or (PW1 and RWTBL2) Common A2h and B2h memory locations Volatile RESERVED RESERVED AEN DAC1EN RESERVED RESERVED BIT 0 SEEB: 0 = (default) Enables EEPROM writes to SEE bytes. 1 = Disables EEPROM writes to SEE bytes during configuration, so that the configuration of the part is not delayed by the EE cycle time. Once the values are known, write this bit to a 0 and write the SEE locations again for data to be written to the EEPROM. DAC2EN: 0 = DAC2 VALUE is writable by the user and the LUT recalls are disabled. This allows users to interactively test their modules by writing the values for DAC2. The output is updated with the new value at the end of the write cycle. The I2C STOP condition is the end of the write cycle. 1 = (default) Enables automatic control of the LUT for DAC2 VALUE. RESERVED AEN: 0 = The temperature-calculated index value TINDEX is writable by the user and the updates of calculated indexes are disabled. This allows the user to interactively test the modules by controlling the indexing for the LUTs. The recalled values from the LUTs appear in the DAC registers after the next completion of a temperature conversion. 1 = (default) The temperature-calculated index value TINDEX is used to control the LUTs. DAC1EN: 0 = DAC1 VALUE is writable by the user and the LUT recalls are disabled. This allows the user to interactively test their modules by writing the values for DAC1. The output is updated with the new value at the end of the write cycle. The I2C STOP condition is the end of the write cycle. 1 = (default) Enables automatic control of the LUT for DAC1 VALUE. BIT 7 BIT 6 BITS 5, 4, 1, 0 BIT 3 BIT 2 43 SFP Controller for Dual Rx Interface DS1877 Table 02h, Register 81h: TEMPERATURE INDEX (TINDEX) FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 81h 27 BIT 7 26 00h PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) (PW2 and AEN = 0) or (PW1 and RWTBL2 and AEN = 0) Common A2h and B2h memory locations Volatile 25 24 23 22 21 20 BIT 0 Holds the calculated index based on the temperature measurement. This index is used for the address during lookup of Table 04h. Temperature measurements below -40NC or above +102NC are clamped to 80h and C7h, respectively. The calculation of TINDEX is as follows: TINDEX = Temp_Value + 40C + 80h 2C TINDEX4 TINDEX3 TINDEX2 TINDEX1 TINDEX0 For the temperature-indexed LUTs (2NC), the index used during the lookup function for each table is as follows: Table 04h (DAC) 1 TINDEX6 TINDEX5 For the 8-position LUT tables, the following table shows the lookup function: TINDEX BYTE TEMP (NC) 1000_0xxx F8 < -8 1001_0xxx F9 -8 to +8 1001_1xxx FA +8 to +24 1010_0xxx FB +24 to +40 1010_1xxx FC +40 to +56 1011_0xxx FD +56 to +72 1011_1xxx FE +72 to +88 11xx_xxxx FF R +88 Table 02h, Register 82h-85h: RESERVED FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE These registers are reserved. 00h N/A N/A N/A N/A Table 02h, Register 86h: DEVICE ID FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 86h 0 BIT 7 Hardwired connections to show the device ID. 1 77h PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) N/A ROM 1 1 0 1 1 1 BIT 0 44 SFP Controller for Dual Rx Interface Table 02h, Register 87h: DEVICE VER FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 87h BIT 7 Hardwired connections to show the device version. DEVICE VERSION PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) N/A ROM DEVICE VERSION BIT 0 DS1877 Table 02h, Register 88h: CNFGA FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 88h RESERVED BIT 7 BITS 7:5, 1 RESERVED ASEL: Address select. 0 = (default) Device address is A2h for receiver 1 and B2h for receiver 2. 1 = DEVICE ADDRESS byte (Table 02h, Register 8Bh) is used as the device address for receiver 1. Receiver 2 remains at B2h. MASK: 0 = (default) Alarm-enable row exists at Table 01h, Registers F8h-FFh. Table 05h, Registers F8h- FFh are empty. 1 = Alarm-enable row exists at Table 05h, Registers F8h-FFh. Table 01h, Registers F8h-FFh are empty. INVRSOUT: Allow for inversion of the RSELOUT pin (see Figure 11). 0 = (default) RSELOUT is not inverted. 1 = RSELOUT is inverted. INVLOSOUT: Allow for inversion of signal driven to the LOSOUT output pin. 0 = (default) LOSOUT is not inverted. 1 = LOSOUT signal is inverted. RESERVED C0h PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) PW2 or (PW1 and RWTBL2) Common A2h and B2h memory locations Nonvolatile (SEE) RESERVED ASEL MASK INVRSOUT RESERVED INVLOSOUT BIT 0 BIT 4 BIT 3 BIT 2 BIT 0 45 SFP Controller for Dual Rx Interface DS1877 Table 02h, Register 89h: CNFGB FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 89h INXC BIT 7 INXC: INX software control bit (see Figure 11). 0 = INX pin's logic controls OUTX pin. 1 = OUTX is active (bit 6 defines the polarity). INVOUTX: Inverts the active state for OUTX (see Figure 11). 0 = Noninverted. 1 = Inverted. ALATCH2: ADC alarm's comparison latch, Lower Memory, Registers 70h-71h. 0 = ADC alarm and flags reflect the status of the last comparison. 1 = ADC alarm flags remain set. QTLATCH2: QT's comparison latch, Lower Memory, Register 73h. 0 = QT alarm and warning flags reflect the status of the last comparison. 1 = QT alarm and warning flags remain set. WLATCH2: ADC warning's comparison latch, Lower Memory, Register 74h. 0 = ADC warning flags reflect the status of the last comparison. 1 = ADC warning flags remain set. ALATCH1: ADC alarm's comparison latch, Lower Memory, Registers 70h-71h. 0 = ADC alarm and flags reflect the status of the last comparison. 1 = ADC alarm flags remain set. QTLATCH1: QT's comparison latch, Lower Memory, Register 73h. 0 = QT alarm and warning flags reflect the status of the last comparison. 1 = QT alarm and warning flags remain set. WLATCH1: ADC warning's comparison latch, Lower Memory, Register 74h. 0 = ADC warning flags reflect the status of the last comparison. 1 = ADC warning flags remain set. INVOUTX 00h PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) PW2 or (PW1 and RWTBL2) Common A2h and B2h memory locations Nonvolatile (SEE) ALATCH2 QTLATCH2 WLATCH2 ALATCH1 QTLATCH1 WLATCH1 BIT 0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 46 SFP Controller for Dual Rx Interface Table 02h, Register 8Ah: CNFGC FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE TXD_RST EN DAC2 00h PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) PW2 or (PW1 and RWTBL2) Common A2h and B2h memory locations Nonvolatile (SEE) TXD_RST EN DAC1 DS1877 8Ah RESERVED BIT 7 BITS 7, 3 BIT 6 LOSC2 INVLOS2 RESERVED LOSC1 INVLOS1 BIT 0 RESERVED TXD_RST EN DAC2: 0 = TXDC2 has no effect on DAC2. 1 = DAC2 is reset by TXDC2. LOSC2: See Figure 11. 0 = LOS2 LO QT drives LOSOUT logic. 1 = LOS2 input pin drives LOSOUT logic. INVLOS2: See Figure 11. 0 = (default) LOS2 input is not inverted. 1 = LOS2 input is inverted. TXD_RST ECN DAC1: See Figure 11. 0 = TXDC1 has no effect on DAC1. 1 = DAC1 is reset by TXDC1. LOSC1: See Figure 11. 0 = LOS1 LO QT drives LOSOUT logic. 1 = LOS1 input pin drives LOSOUT logic. INVLOS1: See Figure 11. 0 = (default) LOS1 input is not inverted. 1 = LOS1 input is inverted. BIT 5 BIT 4 BIT 2 BIT 1 BIT 0 Table 02h, Register 8Bh: DEVICE ADDRESS FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 8Bh RESERVED BIT 7 RESERVED 00h PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) PW2 or (PW1 and RWTBL2) Common A2h and B2h memory locations Nonvolatile (SEE) RESERVED RESERVED 23 22 21 RESERVED BIT 0 This value becomes the I2C slave address for the main memory when the ASEL bit (Table 02h, Register 88h) is set. If A0h/B0h is programmed to this register, the auxiliary memory is disabled. For example, writing xxxx_010x makes the main device addresses A4h and B4h. 47 SFP Controller for Dual Rx Interface DS1877 Table 02h, Register 8Ch: RESERVED FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE These registers are reserved. N/A N/A N/A N/A Table 02h, Register 8Dh: FORCE RSSI FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 8Dh RESERVED BIT 7 BITS 7, 3 BIT 6 RESERVED XOVEREN2: Enables RSSI conversion to use the XOVER2 value during RSSI2 conversions. 0 = Uses hysteresis for linear RSSI measurements. 1 = XOVER1 value is enabled for nonlinear RSSI measurements. RSSI2_FC and RSSI2_FF: RSSI2 force coarse and RSSI2 force fine. Control bits for RSSI mode of operation on the RSSI2 conversion. 00b = (default) Normal RSSI mode of operation. 01b = The fine settings of scale and offset are used for RSSI2 conversions. 10b = The coarse settings of scale and offset are used for RSSI2 conversions. 11b = Normal RSSI mode of operation. XOVEREN1: Enables RSSI conversion to use the XOVER1 value during RSSI1 conversions. 0 = Uses hysteresis for linear RSSI measurements. 1 = XOVER1 value is enabled for nonlinear RSSI measurements. RSSI1_FC and RSSI1_FF: RSSI1 force coarse and RSSI1 force fine. Control bits for RSSI mode of operation on the RSSI1 conversion. 00b = (default) Normal RSSI mode of operation. 01b = The fine settings of scale and offset are used for RSSI1 conversions. 10b = The coarse settings of scale and offset are used for RSSI1 conversions. 11b = Normal RSSI mode of operation. XOVEREN2 00h PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) PW2 or (PW1 and RWTBL2) Common A2h and B2h memory locations Nonvolatile (SEE) RSSI2_FC RSSI2_FF RESERVED XOVEREN1 RSSI1_FC RSSI1_FF BIT 0 BITS 5:4 BIT 2 BITS 1:0 48 SFP Controller for Dual Rx Interface Table 02h, Register 8Eh: RIGHT-SHIFT2 (RSHIFT2) FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 8Eh RESERVED BIT 7 RSSI2C2 00h PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) PW2 or (PW1 and RWTBL2) Common A2h and B2h memory locations Nonvolatile (SEE) RSSI2C1 RSSI2C0 RESERVED RSSI2F2 RSSI2F1 RSSI2F0 BIT 0 DS1877 Allows for right-shifting the final answer of RSSI2 COARSE and RSSI2 FINE. This allows for scaling the measurement to the smallest full-scale voltage and then right-shifting the final result so the reading is weighted to the correct LSB. Table 02h, Register 8Fh: RIGHT-SHIFT1 (RSHIFT1) FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 8Fh RESERVED BIT 7 RSSI1C2 00h PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) PW2 or (PW1 and RWTBL2) Common A2h and B2h memory locations Nonvolatile (SEE) RSSI1C1 RSSI1C0 RESERVED RSSI1F2 RSSI1F1 RSSI1F0 BIT 0 Allows for right-shifting the final answer of RSSI1 COARSE and RSSI1 FINE. This allows for scaling the measurements to the smallest full-scale voltage and then right-shifting the final result so the reading is weighted to the correct LSB. Table 02h, Register 90h-91h: RESERVED FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE These registers are reserved. 00h N/A N/A N/A N/A 49 SFP Controller for Dual Rx Interface DS1877 Table 02h, Register 92h-93h: VCC SCALE Table 02h, Register 94h-95h: XOVER2 COARSE Table 02h, RegisteR 96h-97h: XOVER2 FINE Table 02h, RegisteR 98h-99h: RSSI2 COARSE SCALE Table 02h, Register 9Ah-9Bh: RSSI2 FINE SCALE Table 02h, Register 9Ch-9Dh: RSSI1 COARSE SCALE Table 02h, Register 9Eh-9Fh: RSSI1 FINE SCALE FACTORY CALIBRATED READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 92h, 94h, 96h, 98h, 9Ah, 9Ch, 9Eh 93h, 95h, 97h, 99h, 9Bh, 9Dh, 9Fh PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) PW2 or (PW1 and RWTBL2) Common A2h and B2h memory locations Nonvolatile (SEE) 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20 BIT 7 BIT 0 Controls the scaling or gain of the full-scale voltage measurements. The factory-calibrated value produces an FS voltage of 6.5536V for VCC, 2.5V for RSSI2 COARSE and RSSI1 COARSE, and 0.3125V for RSSI2 FINE and RSSI1 FINE. Table 02h, Register A0h-A1h: INTERNAL TEMP OFFSET FACTORY CALIBRATED READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE A0h A1h S 21 BIT 7 28 20 PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) PW2 or (PW1 and RWTBL2) Common A2h and B2h memory locations Nonvolatile (SEE) 27 2-1 26 2-2 25 2-3 24 2-4 23 2-5 22 2-6 BIT 0 Allows for offset control of temperature measurement if desired. The final result must be XORed with BB40h before writing to this register. Factory calibration contains the desired value for a reading in degrees Celsius. 50 SFP Controller for Dual Rx Interface Table 02h, Register A2h-A3h: VCC OFFSET Table 02h, Register A4h-A5h: XOVER1 COARSE Table 02h, Register A6h-A7h: XOVER1 FINE Table 02h, Register A8h-A9h: RSSI2 COARSE OFFSET Table 02h, Register AAh-ABh: RSSI2 FINE OFFSET Table 02h, Register ACh-ADh: RSSI1 COARSE OFFSET Table 02h, Register AEh-AFh: RSSI1 FINE OFFSET FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE A2h, A4h, A6h, A8h, AAh, ACh, AEh A3h, A5h, A7h, A9h, ABh, ADh, AFh 00h PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) PW2 or (PW1 and RWTBL2) Common A2h and B2h memory locations Nonvolatile (SEE) DS1877 S S 215 214 213 212 211 210 29 28 27 26 25 24 23 22 BIT 7 Allows for offset control of these voltage measurements if desired. This number is two's complement. BIT 0 51 SFP Controller for Dual Rx Interface DS1877 Table 02h, Register B0h-B3h: PW1 FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE B0h B1h B2h B3h 231 223 215 27 BIT 7 230 222 214 26 FFFF FFFFh N/A PW2 or (PW1 and WPW1) Nonvolatile (SEE) 229 221 213 25 228 220 212 24 227 219 211 23 226 218 210 22 225 217 29 21 224 216 28 20 BIT 0 The PWE value is compared against the value written to this location to enable PW1 access. At power-on, the PWE value is set to all ones. Thus, writing these bytes to all ones grants PW1 access on power-on without writing the password entry. All reads of this register are 00h. Table 02h, Register B4h-B7h: PW2 FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE B4h B5h B6h B7h 231 223 215 27 BIT 7 230 222 214 26 FFFF FFFFh N/A PW2 Nonvolatile (SEE) 229 221 213 25 228 220 212 24 227 219 211 23 226 218 210 22 225 217 29 21 224 216 28 20 BIT 0 The PWE value is compared against the value written to this location to enable PW2 access. At power-on, the PWE value is set to all ones. Thus, writing these bytes to all ones grants PW2 access on power-on without writing the password entry. All reads of this register are 00h. 52 SFP Controller for Dual Rx Interface Table 02h, Register B8h: LOS RANGING2 FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE B8h RESERVED BIT 7 This register controls the full-scale range of the QT monitoring for the RSSI2 differential inputs. BITS 7, 3 RESERVED (default = 0) HLOS2[2:0]: HLOS2 full-scale ranging: 3-bit value to select the full-scale comparison voltage for high LOS found on RSSI2. Default is 000b and creates a full scale of 1.25V. HLOS2[2:0] 000b 001b BITS 6:4 010b 011b 100b 101b 110b 111b % OF 1.25V 100.00 80.02 66.69 50.05 40.05 33.38 28.62 25.04 FS VOLTAGE (V) 1.250 1.0003 0.8336 0.6256 0.5006 0.4172 0.3578 0.313 HLOS22 00h PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) PW2 or (PW1 and RWTBL2) Common A2h and B2h memory location Nonvolatile (SEE) HLOS21 HLOS20 RESERVED LLOS22 LLOS21 LLOS20 BIT 0 DS1877 LLOS2[2:0]: LLOS2 full-scale ranging: 3-bit value to select the full-scale comparison voltage for low LOS found on RSSI2. Default is 000b and creates a full scale of 1.25V. LLOS2[2:0] 000b 001b BITS 2:0 010b 011b 100b 101b 110b 111b % OF 1.25V 100.00 80.02 66.69 50.05 40.05 33.38 28.62 25.04 FS VOLTAGE (V) 1.250 1.0003 0.8336 0.6256 0.5006 0.4172 0.3578 0.313 53 SFP Controller for Dual Rx Interface DS1877 Table 02h, Register B9h: RESERVED FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE This register is reserved. 00h N/A N/A N/A N/A Table 02h, Register BAh: HLOS2 FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE BAh 27 BIT 7 26 00h PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) (PW2 and QT2EN = 0) or (PW1 and RWTBL2 and QT2EN = 0) Common A2h and B2h memory locations Nonvolatile (SEE) 25 24 23 22 21 20 BIT 0 Fast comparison DAC threshold adjust for high LOS2. The combination of HLOS2 and LLOS2 creates a hysteresis comparator. As RSSI falls below the LLOS2 threshold, the LOS2 LO alarm bit is set to 1. The LOS2 alarm remains set until the RSSI2 input is found above the HLOS2 threshold setting, which clears the LOS2 LO alarm bit and sets the LOS2 HI alarm bit. Table 02h, Register BBh: LLOS2 FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE BBh 27 BIT 7 26 00h PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) (PW2 and QT2EN = 0) or (PW1 and RWTBL2 and QT2EN = 0) Common A2h and B2h memory locations Nonvolatile (SEE) 25 24 23 22 21 20 BIT 0 Fast comparison DAC threshold adjust for low LOS2. See HLOS2 (Table 02h, Register BAh) for the functional description. 54 SFP Controller for Dual Rx Interface Table 02h, Register BCh: LOS RANGING1 FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE BCh RESERVED BIT 7 This register controls the full-scale range of the QT monitoring for the RSSI1 differential inputs. BITS 7, 3 RESERVED (default = 0) HLOS1[2:0]: HLOS1 full-scale ranging: 3-bit value to select the full-scale comparison voltage for high RSSI1. Default is 000b and creates a full scale of 1.25V. HBIAS1[2:0] 000b 001b BITS 6:4 010b 011b 100b 101b 110b 111b % OF 1.25V 100.00 80.02 66.69 50.05 40.05 33.38 28.62 25.04 FS VOLTAGE (V) 1.250 1.0003 0.8336 0.6256 0.5006 0.4172 0.3578 0.313 HLOS12 00h PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) PW2 or (PW1 and RWTBL2) Common A2h and B2h memory locations Nonvolatile (SEE) HLOS11 HLOS10 RESERVED LLOS12 LLOS11 LLOS10 BIT 0 DS1877 LLOS1[2:0]: LLOS1 full-scale ranging: 3-bit value to select the full-scale comparison voltage for low RSSI1. Default is 000b and creates a full scale of 1.25V. LLOS1[2:0] 000b 001b BITS 2:0 010b 011b 100b 101b 110b 111b % OF 1.25V 100.00 80.02 66.69 50.05 40.05 33.38 28.62 25.04 FS VOLTAGE (V) 1.250 1.0003 0.8336 0.6256 0.5006 0.4172 0.3578 0.313 55 SFP Controller for Dual Rx Interface DS1877 Table 02h, Register BDh: RESERVED FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE This register is reserved. 00h N/A N/A N/A N/A Table 02h, Register BEh: HLOS1 FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE BEh 27 BIT 7 26 00h PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) (PW2 and QT2EN = 0) or (PW1 and RWTBL2 and QT2EN = 0) Common A2h and B2h memory locations Nonvolatile (SEE) 25 24 23 22 21 20 BIT 0 Fast comparison DAC threshold adjust for high LOS1. The combination of HLOS1 and LLOS1 creates a hysteresis comparator. As RSSI falls below the LLOS1 threshold, the LOS1 LO alarm bit is set to 1. The LOS1 alarm remains set until the RSSI1 input is found above the HLOS1 threshold setting, which clears the LOS1 LO alarm bit and sets the LOS1 HI alarm bit. Table 02h, Register BFh: LLOS1 FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE BFh 27 BIT 7 26 00h PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) (PW2 and QT2EN = 0) or (PW1 and RWTBL2 and QT2EN = 0) Common A2h and B2h memory locations Nonvolatile (SEE) 25 24 23 22 21 20 BIT 0 Fast comparison DAC threshold adjust for low LOS1. See HLOS1 (Table 02h, Register BEh) for the functional description. 56 SFP Controller for Dual Rx Interface Table 02h, Register C0h: PW_ENA FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE C0h RESERVED BIT 7 BIT 7 RESERVED RWTBL1C: Table 01h or 05h bytes F8h-FFh. Table address is dependent on MASK bit (Table 02h, Register 88h). 0 = (default) Read and write access for PW2 only. 1 = Read and write access for both PW1 and PW2. RWTBL2: Table 02h. Writing a nonvolatile value to this bit requires PW2 access. 0 = (default) Read and write access for PW2 only. 1 = Read and write access for both PW1 and PW2. RWTBL1A: Table 01h, Registers 80h-BFh. 0 = Read and write access for PW2 only. 1 = (default) Read and write access for both PW1 and PW2. RWTBL1B: Table 01h, Registers C0h-F7h. 0 = (default) Read and write access for PW2 only. 1 = Read and write access for both PW1 and PW2. WLOWER: Bytes 00h-5Fh in main memory. All users can read this area. 0 = (default) Write access for PW2 only. 1 = Write access for both PW1 and PW2. WAUXA: Auxiliary memory, Registers 00h-7Fh. All users can read this area. 0 = (default) Write access for PW2 only. 1 = Write access for both PW1 and PW2. WAUXB: Auxiliary memory, Registers 80h-FFh. All users can read this area. 0 = (default) Write access for PW2 only. 1 = Write access for both PW1 and PW2. RWTBL1C 10h PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) PW2 or (PW1 and RWTBL2) Common A2h and B2h memory locations Nonvolatile (SEE) RWTBL2 RWTBL1A RWTBL1B WLOWER WAUXA WAUXB BIT 0 DS1877 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 57 SFP Controller for Dual Rx Interface DS1877 Table 02h, Register C1h: PW_ENB FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE C1h RWTBL46 BIT 7 RWTBL46: Table 04h. 0 = (default) Read and write access for PW2 only. 1 = Read and write access for PW1 and PW2. RTBL1C: Table 01h or Table 05h, Registers F8h-FFh. Table address is dependent on MASK bit (Table 02h, Register 88h). 0 = (default) Read and write access for PW2 only. 1 = Read access for PW1 and PW2. RTBL2: Table 02h. 0 = (default) Read and write access for PW2 only. 1 = Read access for PW1 and PW2. RTBL1A: Table 01h, Registers 80h-BFh. 0 = (default) Read and write access for PW2 only. 1 = Read access for PW1 and PW2. RTBL1B: Table 01h, Registers C0h-F7h. 0 = (default) Read and write access for PW2 only. 1 = Read access for PW1 and PW2. WPW1: Register PW1 (Table 02h, Registers B0h-B3h). 0 = (default) Write access for PW2 only. 1 = Write access for PW1 and PW2. WAUXAU: Auxiliary memory, Registers 00h-7Fh. All users can read this area. 0 = Write access for PW2 only. 1 = (default) Write access for user, PW1, and PW2. WAUXBU: Auxiliary memory, Registers 80h-FFh. All users can read this area. 0 = Write access for PW2 only. 1 = (default) Write access for user, PW1, and PW2. RTBL1C 03h PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) PW2 or (PW1 and RWTBL2) Common A2h and B2h memory locations Nonvolatile (SEE) RTBL2 RTBL1A RTBL1B WPW1 WAUXAU WAUXBU BIT 0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 58 SFP Controller for Dual Rx Interface Table 02h, Register C2h-C5h: RESERVED FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE These registers are reserved. 00h N/A N/A N/A N/A DS1877 Table 02h, Register C6h: POLARITY FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE C6h RESERVED BIT 7 BITS 7:4, 2, 0 RESERVED 0Ah PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) PW2 or (PW1 and RWTBL2) Common A2h and B2h memory locations Nonvolatile (SEE) RESERVED RESERVED DAC2P RESERVED DAC1P RESERVED BIT 0 RESERVED DAC2P: DAC2 VALUE polarity. The DAC2 VALUE (Table 02h, Registers C8h-C9h) range is 000h-3FFh. A setting of 000h creates a pulse-density of zero and 3FFh creates a pulse-density of 1023/1024. This polarity bit allows the user to use GND or VREFIN as the reference. The power-on of DAC2 VALUE is 000h; thus an application that needs VREFIN to be the off state should use the inverted polarity. 0 = Normal polarity. A setting of 000h results in a pulse-density output of zero held at GND, and a setting of 3FFh results in a pulsed-density output of 1023/1024 held mostly at VREFIN. 1 = Inverted polarity. A setting of 000h results in a pulse-density output of zero held at VREFIN, and a setting of 3FFh results in a pulsed-density output of 1023/1024 held mostly at GND. DAC1P: DAC1 VALUE polarity. The DAC1 VALUE (Table 02h, Registers CCh-CDh) range is 000h-3FFh. A setting of 000h creates a pulse-density of zero and 3FFh creates a pulse-density of 1023/1024. This polarity bit allows the user to use GND or VREFIN as the reference. The power-on of DAC1 VALUE is 000h; thus an application that needs VREFIN to be the off state should use the inverted polarity. 0 = Normal polarity. A setting of 000h results in a pulse-density output of zero held at GND, and a setting of 3FFh results in a pulsed-density output of 1023/1024 held mostly at VREFIN. 1 = Inverted polarity. A setting of 000h results in a pulse-density output of zero held at VREFIN, and a setting of 3FFh results in a pulsed-density output of 1023/1024 held mostly at GND. BIT 3 BIT 1 59 SFP Controller for Dual Rx Interface DS1877 Table 02h, Register C7h: TBLSELPON FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE C7h 27 BIT 7 Chooses the initial value for the TBL SEL byte (Lower Memory, Register 7Fh) at power-on. 26 00h PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) PW2 or (PW1 and RWTBL2) Common A2h and B2h memory locations Nonvolatile (SEE) 25 24 23 22 21 20 BIT 0 Table 02h, Register C8h-C9h: DAC2 VALUE FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE C8h C9h 0 27 BIT 7 0 26 0000h PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) (PW2 and DAC2EN = 0) or (PW1 and RWTBL2 and DAC2EN = 0) Common A2h and B2h memory locations Volatile 0 25 0 24 0 23 0 22 29 21 28 20 BIT 0 The digital value used for DAC2 VALUE. It is the result of LUT4 plus DAC2 OFFSET times 4 recalled from Address B0h, Table 04h (Registers F8h-FFh) at the adjusted memory address found in TINDEX. This register is updated at the end of the temperature conversion. DAC2 VALUE = LUT4 + DAC2 OFFSET x 4 V VDAC2 = REFIN x DAC2 VALUE d (if POLARITY = 0) 1024 V VDAC2 = VREFIN - REFIN x DAC VALUE d (if POLARITY = 1) 1024 Table 02h, Register CAh-CBh: RESERVED FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE These registers do not exist. 00h N/A N/A N/A None 60 SFP Controller for Dual Rx Interface Table 02h, Register CCh-CDh: DAC1 VALUE FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE CCh CDh 0 27 BIT 7 0 26 0000h PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) (PW2 and DAC1EN = 0) or (PW1 and RWTBL2 and DAC1EN = 0) Common A2h and B2h memory locations Volatile 0 25 0 24 0 23 0 22 29 21 28 20 BIT 0 DS1877 The digital value used for DAC1 VALUE. It is the result of LUT4 plus DAC1 OFFSET times 4 recalled from Address A0h, Table 04h (Registers F8h-FFh) at the adjusted memory address found in TINDEX. This register is updated at the end of the temperature conversion. DAC1 VALUE = LUT4 + DAC1 OFFSET x 4 V VDAC1 = REFIN x DAC1 VALUE d (if POLARITY = 0) 1024 V VDAC1 = VREFIN - REFIN x DAC1 VALUE d (if POLARITY = 1) 1024 Table 02h, Register CEh-CFh: RESERVED FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE These registers do not exist. 00h N/A N/A N/A N/A Table 02h, Register D0h-FFh: EMPTY FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE These registers do not exist. 00h N/A N/A N/A None 61 SFP Controller for Dual Rx Interface DS1877 Table 04h Register Descriptions Table 04h, Register 80h-C7h: DAC LUT FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE 80h-C7h 27 BIT 7 26 00h PW2 or (PW1 and RWTBL46) PW2 or (PW1 and RWTBL46) Different A2h and B2h memory locations Nonvolatile (EE) 25 24 23 22 21 20 BIT 0 Digital value for the DAC1 VALUE (A2h address) and DAC2 VALUE (B2h address) outputs. The DAC LUT is a set of registers assigned to hold the temperature profile for the DAC1 and DAC2 values. The temperature measurement is used to index the LUT (TINDEX, Table 02h, Register 81h) in 2NC increments from -40NC to +102NC, starting at 80h. Register 80h defines the -40NC to -38NC DAC output, Register 81h defines -38NC to -36NC DAC output, and so on. Values recalled from this EEPROM memory table are written into the DAC1 and DAC2 value (Table 02h, Registers C8h-C9h, CCh-CDh) locations that hold the values until the next temperature conversion. The device can be placed into a manual mode (DAC1EN and DAC2EN bits, Table 02h, Register 80h), where DAC1 and DAC2 values are directly controlled for calibration. If the temperature compensation functionality is not required, program the entire table to the desired modulation setting. Table 02h, Register C8h-F7h: EMPTY FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE These registers do not exist. 00h N/A N/A N/A None 62 SFP Controller for Dual Rx Interface Table 04h, Register F8h-FFh: DAC OFFSET LUT FACTORY DEFAULT READ ACCESS WRITE ACCESS A2h AND B2h MEMORY MEMORY TYPE F8h-FFh 29 BIT 7 The digital value for the temperature offset of the DAC1 and DAC2 VALUE outputs. F8h F9h FAh FBh FCh FDh FEh FFh Less than or equal to -8NC Greater than -8NC up to +8NC Greater than +8NC up to +24NC Greater than +24NC up to +40NC Greater than +40NC up to +56NC Greater than +56NC up to +72NC Greater than +72NC up to +88NC Greater than +88NC 28 00h PW2 or (PW1 and RWTBL46) PW2 or (PW1 and RWTBL46) Different A2h and B2h memory locations Nonvolatile (EE) 27 26 25 24 23 22 BIT 0 DS1877 The DAC VALUE is a 10-bit value. The DAC LUT is an 8-bit LUT. The DAC OFFSET LUT times 4 plus the DAC LUT makes use of the entire 10-bit range. Auxiliary Memory A0h Register Descriptions Auxiliary Memory A0h, Register 00h-7Fh: EEPROM FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 00h-7Fh 27 BIT 7 Accessible with the slave address A0h. 26 00h All PW2 or (PW1 and WAUXA) or (WAUXAU) Nonvolatile (EE) 25 24 23 22 21 20 BIT 0 63 SFP Controller for Dual Rx Interface DS1877 Auxiliary Memory A0h, Register 80h-FFh: EEPROM FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE 80h-FFh 27 BIT 7 Accessible with the slave address A0h. 26 00h All PW2 or (PW1 and WAUXB) or (WAUXBU) Nonvolatile (EE) 25 24 23 22 21 20 BIT 0 Applications Information To achieve best results, it is recommended that the power supply is decoupled with a 0.01FF or a 0.1FF capacitor. Use high-quality, ceramic, surface-mount capacitors, and mount the capacitors as close as possible to the VCC and GND pins to minimize lead inductance. SDA is an open-collector output on the device that requires a pullup resistor to realize high logic levels. A master using either an open-collector output with a pullup resistor or a push-pull output driver can be used for SCL. Pullup resistor values should be chosen to ensure that the rise and fall times listed in the I2C AC Electrical Characteristics table are within specification. Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 28 TQFN-EP PACKAGE CODE T2855+6 DOCUMENT NO. 21-0140 Power-Supply Decoupling SDA and SCL Pullup Resistors 64 SFP Controller for Dual Rx Interface Revision History REVISION NUMBER 0 1 REVISION DATE 3/10 4/10 Initial release Updated Figure 11 labels for LOS1/2 and INVLOSOUT, and corrected errors in the CNFGC, HLOS2, and HLOS1 bit tables. DESCRIPTION PAGES CHANGED -- 19, 47, 54, 56 DS1877 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 65 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. |
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